cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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omap4-var-som-om44-wlan.dtsi (2246B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (C) 2014 Joachim Eastwood <manabian@gmail.com>
      4 */
      5
      6/ {
      7	/* regulator for wl12xx on sdio4 */
      8	wl12xx_vmmc: wl12xx_vmmc {
      9		pinctrl-names = "default";
     10		pinctrl-0 = <&wl12xx_ctrl_pins>;
     11		compatible = "regulator-fixed";
     12		regulator-name = "vwl1271";
     13		regulator-min-microvolt = <1800000>;
     14		regulator-max-microvolt = <1800000>;
     15		gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;	/* gpio 43 */
     16		startup-delay-us = <70000>;
     17		enable-active-high;
     18	};
     19};
     20
     21&omap4_pmx_core {
     22	uart2_pins: pinmux_uart2_pins {
     23		pinctrl-single,pins = <
     24			OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart2_cts.uart2_cts */
     25			OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0)		/* uart2_rts.uart2_rts */
     26			OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart2_rx.uart2_rx */
     27			OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0)		/* uart2_tx.uart2_tx */
     28		>;
     29	};
     30
     31	wl12xx_ctrl_pins: pinmux_wl12xx_ctrl_pins {
     32		pinctrl-single,pins = <
     33			OMAP4_IOPAD(0x062, PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_a17.gpio_41 (WLAN_IRQ) */
     34			OMAP4_IOPAD(0x064, PIN_OUTPUT | MUX_MODE3)		/* gpmc_a18.gpio_42 (BT_EN) */
     35			OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3)		/* gpmc_a19.gpio_43 (WLAN_EN) */
     36		>;
     37	};
     38
     39	mmc4_pins: pinmux_mmc4_pins {
     40		pinctrl-single,pins = <
     41			OMAP4_IOPAD(0x154, PIN_INPUT_PULLUP | MUX_MODE1)	/* mcspi4_clk.sdmmc4_clk */
     42			OMAP4_IOPAD(0x156, PIN_INPUT_PULLUP | MUX_MODE1)	/* mcspi4_simo.sdmmc4_cmd */
     43			OMAP4_IOPAD(0x158, PIN_INPUT_PULLUP | MUX_MODE1)	/* mcspi4_somi.sdmmc4_dat0 */
     44			OMAP4_IOPAD(0x15e, PIN_INPUT_PULLUP | MUX_MODE1)	/* uart4_tx.sdmmc4_dat1 */
     45			OMAP4_IOPAD(0x15c, PIN_INPUT_PULLUP | MUX_MODE1)	/* uart4_rx.sdmmc4_dat2 */
     46			OMAP4_IOPAD(0x15a, PIN_INPUT_PULLUP | MUX_MODE1)	/* mcspi4_cs0.sdmmc4_dat3 */
     47		>;
     48	};
     49};
     50
     51&uart2 {
     52	pinctrl-names = "default";
     53	pinctrl-0 = <&uart2_pins>;
     54	status = "okay";
     55};
     56
     57&mmc4 {
     58	pinctrl-names = "default";
     59	pinctrl-0 = <&mmc4_pins>;
     60	vmmc-supply = <&wl12xx_vmmc>;
     61	non-removable;
     62	bus-width = <4>;
     63	cap-power-off-card;
     64	status = "okay";
     65
     66	#address-cells = <1>;
     67	#size-cells = <0>;
     68	wlcore: wlcore@2 {
     69		compatible = "ti,wl1271";
     70		reg = <2>;
     71		interrupt-parent = <&gpio2>;
     72		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; /* gpio 41 */
     73		ref-clock-frequency = <38400000>;
     74	};
     75};