cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

orion5x-lacie-ethernet-disk-mini-v2.dts (3580B)

      1/*
      2 * Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
      3 *
      4 * This file is licensed under the terms of the GNU General Public
      5 * License version 2. This program is licensed "as is" without any
      6 * warranty of any kind, whether express or implied.
      7 */
      8
      9/*
     10 * TODO: add Orion USB device port init when kernel.org support is added.
     11 * TODO: add flash write support: see below.
     12 * TODO: add power-off support.
     13 * TODO: add I2C EEPROM support.
     14 */
     15
     16/dts-v1/;
     17
     18#include <dt-bindings/gpio/gpio.h>
     19#include <dt-bindings/input/input.h>
     20#include <dt-bindings/interrupt-controller/irq.h>
     21#include "orion5x-mv88f5182.dtsi"
     22
     23/ {
     24	model = "LaCie Ethernet Disk mini V2";
     25	compatible = "lacie,ethernet-disk-mini-v2", "marvell,orion5x-88f5182", "marvell,orion5x";
     26
     27	memory {
     28		device_type = "memory";
     29		reg = <0x00000000 0x4000000>; /* 64 MB */
     30	};
     31
     32	chosen {
     33		bootargs = "console=ttyS0,115200n8 earlyprintk";
     34		stdout-path = &uart0;
     35	};
     36
     37	soc {
     38		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
     39			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
     40			 <MBUS_ID(0x01, 0x0f) 0 0xfff80000 0x80000>;
     41	};
     42
     43	gpio-keys {
     44		compatible = "gpio-keys";
     45		pinctrl-0 = <&pmx_power_button>;
     46		pinctrl-names = "default";
     47		#address-cells = <1>;
     48		#size-cells = <0>;
     49		button@1 {
     50			label = "Power-on Switch";
     51			linux,code = <KEY_POWER>;
     52			gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
     53		};
     54	};
     55
     56	gpio-leds {
     57		compatible = "gpio-leds";
     58		pinctrl-0 = <&pmx_power_led>;
     59		pinctrl-names = "default";
     60
     61		led@1 {
     62			label = "power:blue";
     63			gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
     64		};
     65	};
     66};
     67
     68&devbus_bootcs {
     69	status = "okay";
     70
     71	/* Read parameters */
     72	devbus,bus-width    = <8>;
     73	devbus,turn-off-ps  = <90000>;
     74	devbus,badr-skew-ps = <0>;
     75	devbus,acc-first-ps = <186000>;
     76	devbus,acc-next-ps  = <186000>;
     77
     78	/* Write parameters */
     79	devbus,wr-high-ps  = <90000>;
     80	devbus,wr-low-ps   = <90000>;
     81	devbus,ale-wr-ps   = <90000>;
     82
     83	/*
     84	 * Currently the MTD code does not recognize the MX29LV400CBCT
     85	 * as a bottom-type device. This could cause risks of
     86	 * accidentally erasing critical flash sectors. We thus define
     87	 * a single, write-protected partition covering the whole
     88	 * flash.  TODO: once the flash part TOP/BOTTOM detection
     89	 * issue is sorted out in the MTD code, break this into at
     90	 * least three partitions: 'u-boot code', 'u-boot environment'
     91	 * and 'whatever is left'.
     92	 */
     93	flash@0 {
     94		compatible = "cfi-flash";
     95		reg = <0 0x80000>;
     96		bank-width = <1>;
     97		#address-cells = <1>;
     98		#size-cells = <1>;
     99
    100		partition@0 {
    101			label = "Full512Kb";
    102			reg = <0 0x80000>;
    103			read-only;
    104		};
    105	};
    106};
    107
    108&ehci0 {
    109	status = "okay";
    110};
    111
    112&eth {
    113	status = "okay";
    114
    115	ethernet-port@0 {
    116		phy-handle = <&ethphy>;
    117	};
    118};
    119
    120&i2c {
    121	status = "okay";
    122	clock-frequency = <100000>;
    123	#address-cells = <1>;
    124
    125	rtc@32 {
    126		compatible = "ricoh,rs5c372a";
    127		reg = <0x32>;
    128		interrupt-parent = <&gpio0>;
    129		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
    130	};
    131};
    132
    133&mdio {
    134	status = "okay";
    135
    136	ethphy: ethernet-phy {
    137		reg = <8>;
    138	};
    139};
    140
    141&pinctrl {
    142	pinctrl-0 = <&pmx_rtc &pmx_power_led_ctrl>;
    143	pinctrl-names = "default";
    144
    145	pmx_power_button: pmx-power-button {
    146		marvell,pins = "mpp18";
    147		marvell,function = "gpio";
    148	};
    149
    150	pmx_power_led: pmx-power-led {
    151		marvell,pins = "mpp16";
    152		marvell,function = "gpio";
    153	};
    154
    155	pmx_power_led_ctrl: pmx-power-led-ctrl {
    156		marvell,pins = "mpp17";
    157		marvell,function = "gpio";
    158	};
    159
    160	pmx_rtc: pmx-rtc {
    161		marvell,pins = "mpp3";
    162		marvell,function = "gpio";
    163	};
    164};
    165
    166&sata {
    167	pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
    168	pinctrl-names = "default";
    169	status = "okay";
    170	nr-ports = <2>;
    171};
    172
    173&uart0 {
    174	status = "okay";
    175};