cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pxa25x.dtsi (2585B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Copyright (C) 2016 Robert Jarzmik <robert.jarzmik@free.fr>
      4 */
      5#include "pxa2xx.dtsi"
      6#include "dt-bindings/clock/pxa-clock.h"
      7
      8/ {
      9	model = "Marvell PXA25x family SoC";
     10	compatible = "marvell,pxa250";
     11
     12	clocks {
     13	       /*
     14		* The muxing of external clocks/internal dividers for osc* clock
     15		* sources has been hidden under the carpet by now.
     16		*/
     17		#address-cells = <1>;
     18		#size-cells = <1>;
     19		ranges;
     20
     21		clks: pxa2xx_clks@41300004 {
     22			compatible = "marvell,pxa250-core-clocks";
     23			#clock-cells = <1>;
     24			status = "okay";
     25		};
     26
     27		/* timer oscillator */
     28		clktimer: oscillator {
     29			compatible = "fixed-clock";
     30			#clock-cells = <0>;
     31			clock-frequency  = <3686400>;
     32			clock-output-names = "ostimer";
     33		};
     34	};
     35
     36	pxabus {
     37		pdma: dma-controller@40000000 {
     38			compatible = "marvell,pdma-1.0";
     39			reg = <0x40000000 0x10000>;
     40			interrupts = <25>;
     41			#dma-cells = <2>;
     42			/* For backwards compatibility: */
     43			#dma-channels = <16>;
     44			dma-channels = <16>;
     45			#dma-requests = <40>;
     46			dma-requests = <40>;
     47			status = "okay";
     48		};
     49
     50		pxairq: interrupt-controller@40d00000 {
     51			marvell,intc-priority;
     52			marvell,intc-nr-irqs = <32>;
     53		};
     54
     55		pinctrl: pinctrl@40e00000 {
     56			reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4
     57			       0x40f00020 0x10>;
     58			compatible = "marvell,pxa25x-pinctrl";
     59		};
     60
     61		gpio: gpio@40e00000 {
     62			compatible = "intel,pxa25x-gpio";
     63			gpio-ranges = <&pinctrl 0 0 84>;
     64			clocks = <&clks CLK_NONE>;
     65		};
     66
     67		pwm0: pwm@40b00000 {
     68			compatible = "marvell,pxa250-pwm";
     69			reg = <0x40b00000 0x10>;
     70			#pwm-cells = <1>;
     71			clocks = <&clks CLK_PWM0>;
     72		};
     73
     74		pwm1: pwm@40b00010 {
     75			compatible = "marvell,pxa250-pwm";
     76			reg = <0x40b00010 0x10>;
     77			#pwm-cells = <1>;
     78			clocks = <&clks CLK_PWM1>;
     79		};
     80
     81		rtc@40900000 {
     82			clocks = <&clks CLK_OSC32k768>;
     83		};
     84	};
     85
     86	timer@40a00000 {
     87		compatible = "marvell,pxa-timer";
     88		reg = <0x40a00000 0x20>;
     89		interrupts = <26>;
     90		clocks = <&clktimer>;
     91		status = "okay";
     92	};
     93
     94	pxa250_opp_table: opp_table0 {
     95		compatible = "operating-points-v2";
     96
     97		opp-99532800 {
     98			opp-hz = /bits/ 64 <99532800>;
     99			opp-microvolt = <1000000 950000 1650000>;
    100			clock-latency-ns = <20>;
    101		};
    102		opp-199065600 {
    103			opp-hz = /bits/ 64 <199065600>;
    104			opp-microvolt = <1000000 950000 1650000>;
    105			clock-latency-ns = <20>;
    106		};
    107		opp-298598400 {
    108			opp-hz = /bits/ 64 <298598400>;
    109			opp-microvolt = <1100000 1045000 1650000>;
    110			clock-latency-ns = <20>;
    111		};
    112		opp-398131200 {
    113			opp-hz = /bits/ 64 <398131200>;
    114			opp-microvolt = <1300000 1235000 1650000>;
    115			clock-latency-ns = <20>;
    116		};
    117	};
    118};