qcom-apq8064.dtsi (39007B)
1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/clock/qcom,gcc-msm8960.h> 5#include <dt-bindings/reset/qcom,gcc-msm8960.h> 6#include <dt-bindings/clock/qcom,mmcc-msm8960.h> 7#include <dt-bindings/clock/qcom,rpmcc.h> 8#include <dt-bindings/soc/qcom,gsbi.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 model = "Qualcomm APQ8064"; 15 compatible = "qcom,apq8064"; 16 interrupt-parent = <&intc>; 17 18 reserved-memory { 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges; 22 23 smem_region: smem@80000000 { 24 reg = <0x80000000 0x200000>; 25 no-map; 26 }; 27 28 wcnss_mem: wcnss@8f000000 { 29 reg = <0x8f000000 0x700000>; 30 no-map; 31 }; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 CPU0: cpu@0 { 39 compatible = "qcom,krait"; 40 enable-method = "qcom,kpss-acc-v1"; 41 device_type = "cpu"; 42 reg = <0>; 43 next-level-cache = <&L2>; 44 qcom,acc = <&acc0>; 45 qcom,saw = <&saw0>; 46 cpu-idle-states = <&CPU_SPC>; 47 }; 48 49 CPU1: cpu@1 { 50 compatible = "qcom,krait"; 51 enable-method = "qcom,kpss-acc-v1"; 52 device_type = "cpu"; 53 reg = <1>; 54 next-level-cache = <&L2>; 55 qcom,acc = <&acc1>; 56 qcom,saw = <&saw1>; 57 cpu-idle-states = <&CPU_SPC>; 58 }; 59 60 CPU2: cpu@2 { 61 compatible = "qcom,krait"; 62 enable-method = "qcom,kpss-acc-v1"; 63 device_type = "cpu"; 64 reg = <2>; 65 next-level-cache = <&L2>; 66 qcom,acc = <&acc2>; 67 qcom,saw = <&saw2>; 68 cpu-idle-states = <&CPU_SPC>; 69 }; 70 71 CPU3: cpu@3 { 72 compatible = "qcom,krait"; 73 enable-method = "qcom,kpss-acc-v1"; 74 device_type = "cpu"; 75 reg = <3>; 76 next-level-cache = <&L2>; 77 qcom,acc = <&acc3>; 78 qcom,saw = <&saw3>; 79 cpu-idle-states = <&CPU_SPC>; 80 }; 81 82 L2: l2-cache { 83 compatible = "cache"; 84 cache-level = <2>; 85 }; 86 87 idle-states { 88 CPU_SPC: spc { 89 compatible = "qcom,idle-state-spc", 90 "arm,idle-state"; 91 entry-latency-us = <400>; 92 exit-latency-us = <900>; 93 min-residency-us = <3000>; 94 }; 95 }; 96 }; 97 98 memory@0 { 99 device_type = "memory"; 100 reg = <0x0 0x0>; 101 }; 102 103 thermal-zones { 104 cpu0-thermal { 105 polling-delay-passive = <250>; 106 polling-delay = <1000>; 107 108 thermal-sensors = <&gcc 7>; 109 coefficients = <1199 0>; 110 111 trips { 112 cpu_alert0: trip0 { 113 temperature = <75000>; 114 hysteresis = <2000>; 115 type = "passive"; 116 }; 117 cpu_crit0: trip1 { 118 temperature = <110000>; 119 hysteresis = <2000>; 120 type = "critical"; 121 }; 122 }; 123 }; 124 125 cpu1-thermal { 126 polling-delay-passive = <250>; 127 polling-delay = <1000>; 128 129 thermal-sensors = <&gcc 8>; 130 coefficients = <1132 0>; 131 132 trips { 133 cpu_alert1: trip0 { 134 temperature = <75000>; 135 hysteresis = <2000>; 136 type = "passive"; 137 }; 138 cpu_crit1: trip1 { 139 temperature = <110000>; 140 hysteresis = <2000>; 141 type = "critical"; 142 }; 143 }; 144 }; 145 146 cpu2-thermal { 147 polling-delay-passive = <250>; 148 polling-delay = <1000>; 149 150 thermal-sensors = <&gcc 9>; 151 coefficients = <1199 0>; 152 153 trips { 154 cpu_alert2: trip0 { 155 temperature = <75000>; 156 hysteresis = <2000>; 157 type = "passive"; 158 }; 159 cpu_crit2: trip1 { 160 temperature = <110000>; 161 hysteresis = <2000>; 162 type = "critical"; 163 }; 164 }; 165 }; 166 167 cpu3-thermal { 168 polling-delay-passive = <250>; 169 polling-delay = <1000>; 170 171 thermal-sensors = <&gcc 10>; 172 coefficients = <1132 0>; 173 174 trips { 175 cpu_alert3: trip0 { 176 temperature = <75000>; 177 hysteresis = <2000>; 178 type = "passive"; 179 }; 180 cpu_crit3: trip1 { 181 temperature = <110000>; 182 hysteresis = <2000>; 183 type = "critical"; 184 }; 185 }; 186 }; 187 }; 188 189 cpu-pmu { 190 compatible = "qcom,krait-pmu"; 191 interrupts = <1 10 0x304>; 192 }; 193 194 clocks { 195 cxo_board: cxo_board { 196 compatible = "fixed-clock"; 197 #clock-cells = <0>; 198 clock-frequency = <19200000>; 199 }; 200 201 pxo_board: pxo_board { 202 compatible = "fixed-clock"; 203 #clock-cells = <0>; 204 clock-frequency = <27000000>; 205 }; 206 207 sleep_clk: sleep_clk { 208 compatible = "fixed-clock"; 209 #clock-cells = <0>; 210 clock-frequency = <32768>; 211 }; 212 }; 213 214 sfpb_mutex: hwmutex { 215 compatible = "qcom,sfpb-mutex"; 216 syscon = <&sfpb_wrapper_mutex 0x604 0x4>; 217 #hwlock-cells = <1>; 218 }; 219 220 smem { 221 compatible = "qcom,smem"; 222 memory-region = <&smem_region>; 223 224 hwlocks = <&sfpb_mutex 3>; 225 }; 226 227 smd { 228 compatible = "qcom,smd"; 229 230 modem-edge { 231 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>; 232 233 qcom,ipc = <&l2cc 8 3>; 234 qcom,smd-edge = <0>; 235 236 status = "disabled"; 237 }; 238 239 q6-edge { 240 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; 241 242 qcom,ipc = <&l2cc 8 15>; 243 qcom,smd-edge = <1>; 244 245 status = "disabled"; 246 }; 247 248 dsps-edge { 249 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>; 250 251 qcom,ipc = <&sps_sic_non_secure 0x4080 0>; 252 qcom,smd-edge = <3>; 253 254 status = "disabled"; 255 }; 256 257 riva-edge { 258 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>; 259 260 qcom,ipc = <&l2cc 8 25>; 261 qcom,smd-edge = <6>; 262 263 status = "disabled"; 264 }; 265 }; 266 267 smsm { 268 compatible = "qcom,smsm"; 269 270 #address-cells = <1>; 271 #size-cells = <0>; 272 273 qcom,ipc-1 = <&l2cc 8 4>; 274 qcom,ipc-2 = <&l2cc 8 14>; 275 qcom,ipc-3 = <&l2cc 8 23>; 276 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; 277 278 apps_smsm: apps@0 { 279 reg = <0>; 280 #qcom,smem-state-cells = <1>; 281 }; 282 283 modem_smsm: modem@1 { 284 reg = <1>; 285 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>; 286 287 interrupt-controller; 288 #interrupt-cells = <2>; 289 }; 290 291 q6_smsm: q6@2 { 292 reg = <2>; 293 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>; 294 295 interrupt-controller; 296 #interrupt-cells = <2>; 297 }; 298 299 wcnss_smsm: wcnss@3 { 300 reg = <3>; 301 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>; 302 303 interrupt-controller; 304 #interrupt-cells = <2>; 305 }; 306 307 dsps_smsm: dsps@4 { 308 reg = <4>; 309 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>; 310 311 interrupt-controller; 312 #interrupt-cells = <2>; 313 }; 314 }; 315 316 firmware { 317 scm { 318 compatible = "qcom,scm-apq8064"; 319 320 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; 321 clock-names = "core"; 322 }; 323 }; 324 325 326 /* 327 * These channels from the ADC are simply hardware monitors. 328 * That is why the ADC is referred to as "HKADC" - HouseKeeping 329 * ADC. 330 */ 331 iio-hwmon { 332 compatible = "iio-hwmon"; 333 io-channels = <&xoadc 0x00 0x01>, /* Battery */ 334 <&xoadc 0x00 0x02>, /* DC in (charger) */ 335 <&xoadc 0x00 0x04>, /* VPH the main system voltage */ 336 <&xoadc 0x00 0x0b>, /* Die temperature */ 337 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ 338 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ 339 <&xoadc 0x00 0x0e>; /* Charger temperature */ 340 }; 341 342 soc: soc { 343 #address-cells = <1>; 344 #size-cells = <1>; 345 ranges; 346 compatible = "simple-bus"; 347 348 tlmm_pinmux: pinctrl@800000 { 349 compatible = "qcom,apq8064-pinctrl"; 350 reg = <0x800000 0x4000>; 351 352 gpio-controller; 353 gpio-ranges = <&tlmm_pinmux 0 0 90>; 354 #gpio-cells = <2>; 355 interrupt-controller; 356 #interrupt-cells = <2>; 357 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; 358 359 pinctrl-names = "default"; 360 pinctrl-0 = <&ps_hold>; 361 }; 362 363 sfpb_wrapper_mutex: syscon@1200000 { 364 compatible = "syscon"; 365 reg = <0x01200000 0x8000>; 366 }; 367 368 intc: interrupt-controller@2000000 { 369 compatible = "qcom,msm-qgic2"; 370 interrupt-controller; 371 #interrupt-cells = <3>; 372 reg = <0x02000000 0x1000>, 373 <0x02002000 0x1000>; 374 }; 375 376 timer@200a000 { 377 compatible = "qcom,kpss-timer", 378 "qcom,kpss-wdt-apq8064", "qcom,msm-timer"; 379 interrupts = <1 1 0x301>, 380 <1 2 0x301>, 381 <1 3 0x301>; 382 reg = <0x0200a000 0x100>; 383 clock-frequency = <27000000>, 384 <32768>; 385 cpu-offset = <0x80000>; 386 }; 387 388 acc0: clock-controller@2088000 { 389 compatible = "qcom,kpss-acc-v1"; 390 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 391 }; 392 393 acc1: clock-controller@2098000 { 394 compatible = "qcom,kpss-acc-v1"; 395 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 396 }; 397 398 acc2: clock-controller@20a8000 { 399 compatible = "qcom,kpss-acc-v1"; 400 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; 401 }; 402 403 acc3: clock-controller@20b8000 { 404 compatible = "qcom,kpss-acc-v1"; 405 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; 406 }; 407 408 saw0: power-controller@2089000 { 409 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 410 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 411 regulator; 412 }; 413 414 saw1: power-controller@2099000 { 415 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 416 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 417 regulator; 418 }; 419 420 saw2: power-controller@20a9000 { 421 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 422 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; 423 regulator; 424 }; 425 426 saw3: power-controller@20b9000 { 427 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 428 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; 429 regulator; 430 }; 431 432 sps_sic_non_secure: sps-sic-non-secure@12100000 { 433 compatible = "syscon"; 434 reg = <0x12100000 0x10000>; 435 }; 436 437 gsbi1: gsbi@12440000 { 438 status = "disabled"; 439 compatible = "qcom,gsbi-v1.0.0"; 440 cell-index = <1>; 441 reg = <0x12440000 0x100>; 442 clocks = <&gcc GSBI1_H_CLK>; 443 clock-names = "iface"; 444 #address-cells = <1>; 445 #size-cells = <1>; 446 ranges; 447 448 syscon-tcsr = <&tcsr>; 449 450 gsbi1_serial: serial@12450000 { 451 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 452 reg = <0x12450000 0x100>, 453 <0x12400000 0x03>; 454 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; 456 clock-names = "core", "iface"; 457 status = "disabled"; 458 }; 459 460 gsbi1_i2c: i2c@12460000 { 461 compatible = "qcom,i2c-qup-v1.1.1"; 462 pinctrl-0 = <&i2c1_pins>; 463 pinctrl-1 = <&i2c1_pins_sleep>; 464 pinctrl-names = "default", "sleep"; 465 reg = <0x12460000 0x1000>; 466 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 468 clock-names = "core", "iface"; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 status = "disabled"; 472 }; 473 474 }; 475 476 gsbi2: gsbi@12480000 { 477 status = "disabled"; 478 compatible = "qcom,gsbi-v1.0.0"; 479 cell-index = <2>; 480 reg = <0x12480000 0x100>; 481 clocks = <&gcc GSBI2_H_CLK>; 482 clock-names = "iface"; 483 #address-cells = <1>; 484 #size-cells = <1>; 485 ranges; 486 487 syscon-tcsr = <&tcsr>; 488 489 gsbi2_i2c: i2c@124a0000 { 490 compatible = "qcom,i2c-qup-v1.1.1"; 491 reg = <0x124a0000 0x1000>; 492 pinctrl-0 = <&i2c2_pins>; 493 pinctrl-1 = <&i2c2_pins_sleep>; 494 pinctrl-names = "default", "sleep"; 495 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 497 clock-names = "core", "iface"; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 status = "disabled"; 501 }; 502 }; 503 504 gsbi3: gsbi@16200000 { 505 status = "disabled"; 506 compatible = "qcom,gsbi-v1.0.0"; 507 cell-index = <3>; 508 reg = <0x16200000 0x100>; 509 clocks = <&gcc GSBI3_H_CLK>; 510 clock-names = "iface"; 511 #address-cells = <1>; 512 #size-cells = <1>; 513 ranges; 514 gsbi3_i2c: i2c@16280000 { 515 compatible = "qcom,i2c-qup-v1.1.1"; 516 pinctrl-0 = <&i2c3_pins>; 517 pinctrl-1 = <&i2c3_pins_sleep>; 518 pinctrl-names = "default", "sleep"; 519 reg = <0x16280000 0x1000>; 520 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&gcc GSBI3_QUP_CLK>, 522 <&gcc GSBI3_H_CLK>; 523 clock-names = "core", "iface"; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 status = "disabled"; 527 }; 528 }; 529 530 gsbi4: gsbi@16300000 { 531 status = "disabled"; 532 compatible = "qcom,gsbi-v1.0.0"; 533 cell-index = <4>; 534 reg = <0x16300000 0x03>; 535 clocks = <&gcc GSBI4_H_CLK>; 536 clock-names = "iface"; 537 #address-cells = <1>; 538 #size-cells = <1>; 539 ranges; 540 541 gsbi4_i2c: i2c@16380000 { 542 compatible = "qcom,i2c-qup-v1.1.1"; 543 pinctrl-0 = <&i2c4_pins>; 544 pinctrl-1 = <&i2c4_pins_sleep>; 545 pinctrl-names = "default", "sleep"; 546 reg = <0x16380000 0x1000>; 547 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&gcc GSBI4_QUP_CLK>, 549 <&gcc GSBI4_H_CLK>; 550 clock-names = "core", "iface"; 551 status = "disabled"; 552 }; 553 }; 554 555 gsbi5: gsbi@1a200000 { 556 status = "disabled"; 557 compatible = "qcom,gsbi-v1.0.0"; 558 cell-index = <5>; 559 reg = <0x1a200000 0x03>; 560 clocks = <&gcc GSBI5_H_CLK>; 561 clock-names = "iface"; 562 #address-cells = <1>; 563 #size-cells = <1>; 564 ranges; 565 566 gsbi5_serial: serial@1a240000 { 567 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 568 reg = <0x1a240000 0x100>, 569 <0x1a200000 0x03>; 570 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; 571 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 572 clock-names = "core", "iface"; 573 status = "disabled"; 574 }; 575 576 gsbi5_spi: spi@1a280000 { 577 compatible = "qcom,spi-qup-v1.1.1"; 578 reg = <0x1a280000 0x1000>; 579 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; 580 pinctrl-0 = <&spi5_default>; 581 pinctrl-1 = <&spi5_sleep>; 582 pinctrl-names = "default", "sleep"; 583 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 584 clock-names = "core", "iface"; 585 status = "disabled"; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 }; 589 }; 590 591 gsbi6: gsbi@16500000 { 592 status = "disabled"; 593 compatible = "qcom,gsbi-v1.0.0"; 594 cell-index = <6>; 595 reg = <0x16500000 0x03>; 596 clocks = <&gcc GSBI6_H_CLK>; 597 clock-names = "iface"; 598 #address-cells = <1>; 599 #size-cells = <1>; 600 ranges; 601 602 gsbi6_serial: serial@16540000 { 603 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 604 reg = <0x16540000 0x100>, 605 <0x16500000 0x03>; 606 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; 608 clock-names = "core", "iface"; 609 status = "disabled"; 610 }; 611 612 gsbi6_i2c: i2c@16580000 { 613 compatible = "qcom,i2c-qup-v1.1.1"; 614 pinctrl-0 = <&i2c6_pins>; 615 pinctrl-1 = <&i2c6_pins_sleep>; 616 pinctrl-names = "default", "sleep"; 617 reg = <0x16580000 0x1000>; 618 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&gcc GSBI6_QUP_CLK>, 620 <&gcc GSBI6_H_CLK>; 621 clock-names = "core", "iface"; 622 status = "disabled"; 623 }; 624 }; 625 626 gsbi7: gsbi@16600000 { 627 status = "disabled"; 628 compatible = "qcom,gsbi-v1.0.0"; 629 cell-index = <7>; 630 reg = <0x16600000 0x100>; 631 clocks = <&gcc GSBI7_H_CLK>; 632 clock-names = "iface"; 633 #address-cells = <1>; 634 #size-cells = <1>; 635 ranges; 636 syscon-tcsr = <&tcsr>; 637 638 gsbi7_serial: serial@16640000 { 639 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 640 reg = <0x16640000 0x1000>, 641 <0x16600000 0x1000>; 642 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 644 clock-names = "core", "iface"; 645 status = "disabled"; 646 }; 647 648 gsbi7_i2c: i2c@16680000 { 649 compatible = "qcom,i2c-qup-v1.1.1"; 650 pinctrl-0 = <&i2c7_pins>; 651 pinctrl-1 = <&i2c7_pins_sleep>; 652 pinctrl-names = "default", "sleep"; 653 reg = <0x16680000 0x1000>; 654 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&gcc GSBI7_QUP_CLK>, 656 <&gcc GSBI7_H_CLK>; 657 clock-names = "core", "iface"; 658 status = "disabled"; 659 }; 660 }; 661 662 rng@1a500000 { 663 compatible = "qcom,prng"; 664 reg = <0x1a500000 0x200>; 665 clocks = <&gcc PRNG_CLK>; 666 clock-names = "core"; 667 }; 668 669 ssbi@c00000 { 670 compatible = "qcom,ssbi"; 671 reg = <0x00c00000 0x1000>; 672 qcom,controller-type = "pmic-arbiter"; 673 674 pm8821: pmic@1 { 675 compatible = "qcom,pm8821"; 676 interrupt-parent = <&tlmm_pinmux>; 677 interrupts = <76 IRQ_TYPE_LEVEL_LOW>; 678 #interrupt-cells = <2>; 679 interrupt-controller; 680 #address-cells = <1>; 681 #size-cells = <0>; 682 683 pm8821_mpps: mpps@50 { 684 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp"; 685 reg = <0x50>; 686 interrupt-controller; 687 #interrupt-cells = <2>; 688 gpio-controller; 689 #gpio-cells = <2>; 690 gpio-ranges = <&pm8821_mpps 0 0 4>; 691 }; 692 }; 693 }; 694 695 qcom,ssbi@500000 { 696 compatible = "qcom,ssbi"; 697 reg = <0x00500000 0x1000>; 698 qcom,controller-type = "pmic-arbiter"; 699 700 pmicintc: pmic@0 { 701 compatible = "qcom,pm8921"; 702 interrupt-parent = <&tlmm_pinmux>; 703 interrupts = <74 8>; 704 #interrupt-cells = <2>; 705 interrupt-controller; 706 #address-cells = <1>; 707 #size-cells = <0>; 708 709 pm8921_gpio: gpio@150 { 710 711 compatible = "qcom,pm8921-gpio", 712 "qcom,ssbi-gpio"; 713 reg = <0x150>; 714 interrupt-controller; 715 #interrupt-cells = <2>; 716 gpio-controller; 717 gpio-ranges = <&pm8921_gpio 0 0 44>; 718 #gpio-cells = <2>; 719 720 }; 721 722 pm8921_mpps: mpps@50 { 723 compatible = "qcom,pm8921-mpp", 724 "qcom,ssbi-mpp"; 725 reg = <0x50>; 726 gpio-controller; 727 #gpio-cells = <2>; 728 gpio-ranges = <&pm8921_mpps 0 0 12>; 729 interrupt-controller; 730 #interrupt-cells = <2>; 731 }; 732 733 rtc@11d { 734 compatible = "qcom,pm8921-rtc"; 735 interrupt-parent = <&pmicintc>; 736 interrupts = <39 1>; 737 reg = <0x11d>; 738 allow-set-time; 739 }; 740 741 pwrkey@1c { 742 compatible = "qcom,pm8921-pwrkey"; 743 reg = <0x1c>; 744 interrupt-parent = <&pmicintc>; 745 interrupts = <50 1>, <51 1>; 746 debounce = <15625>; 747 pull-up; 748 }; 749 750 xoadc: xoadc@197 { 751 compatible = "qcom,pm8921-adc"; 752 reg = <197>; 753 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>; 754 #address-cells = <2>; 755 #size-cells = <0>; 756 #io-channel-cells = <2>; 757 758 vcoin: adc-channel@0 { 759 reg = <0x00 0x00>; 760 }; 761 vbat: adc-channel@1 { 762 reg = <0x00 0x01>; 763 }; 764 dcin: adc-channel@2 { 765 reg = <0x00 0x02>; 766 }; 767 vph_pwr: adc-channel@4 { 768 reg = <0x00 0x04>; 769 }; 770 batt_therm: adc-channel@8 { 771 reg = <0x00 0x08>; 772 }; 773 batt_id: adc-channel@9 { 774 reg = <0x00 0x09>; 775 }; 776 usb_vbus: adc-channel@a { 777 reg = <0x00 0x0a>; 778 }; 779 die_temp: adc-channel@b { 780 reg = <0x00 0x0b>; 781 }; 782 ref_625mv: adc-channel@c { 783 reg = <0x00 0x0c>; 784 }; 785 ref_1250mv: adc-channel@d { 786 reg = <0x00 0x0d>; 787 }; 788 chg_temp: adc-channel@e { 789 reg = <0x00 0x0e>; 790 }; 791 ref_muxoff: adc-channel@f { 792 reg = <0x00 0x0f>; 793 }; 794 }; 795 }; 796 }; 797 798 qfprom: qfprom@700000 { 799 compatible = "qcom,qfprom"; 800 reg = <0x00700000 0x1000>; 801 #address-cells = <1>; 802 #size-cells = <1>; 803 ranges; 804 tsens_calib: calib { 805 reg = <0x404 0x10>; 806 }; 807 tsens_backup: backup_calib { 808 reg = <0x414 0x10>; 809 }; 810 }; 811 812 gcc: clock-controller@900000 { 813 compatible = "qcom,gcc-apq8064"; 814 reg = <0x00900000 0x4000>; 815 nvmem-cells = <&tsens_calib>, <&tsens_backup>; 816 nvmem-cell-names = "calib", "calib_backup"; 817 #clock-cells = <1>; 818 #power-domain-cells = <1>; 819 #reset-cells = <1>; 820 #thermal-sensor-cells = <1>; 821 }; 822 823 lcc: clock-controller@28000000 { 824 compatible = "qcom,lcc-apq8064"; 825 reg = <0x28000000 0x1000>; 826 #clock-cells = <1>; 827 #reset-cells = <1>; 828 }; 829 830 mmcc: clock-controller@4000000 { 831 compatible = "qcom,mmcc-apq8064"; 832 reg = <0x4000000 0x1000>; 833 #clock-cells = <1>; 834 #power-domain-cells = <1>; 835 #reset-cells = <1>; 836 }; 837 838 l2cc: clock-controller@2011000 { 839 compatible = "qcom,kpss-gcc", "syscon"; 840 reg = <0x2011000 0x1000>; 841 }; 842 843 rpm@108000 { 844 compatible = "qcom,rpm-apq8064"; 845 reg = <0x108000 0x1000>; 846 qcom,ipc = <&l2cc 0x8 2>; 847 848 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 849 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 850 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 851 interrupt-names = "ack", "err", "wakeup"; 852 853 rpmcc: clock-controller { 854 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; 855 #clock-cells = <1>; 856 }; 857 858 regulators { 859 compatible = "qcom,rpm-pm8921-regulators"; 860 861 pm8921_s1: s1 {}; 862 pm8921_s2: s2 {}; 863 pm8921_s3: s3 {}; 864 pm8921_s4: s4 {}; 865 pm8921_s7: s7 {}; 866 pm8921_s8: s8 {}; 867 868 pm8921_l1: l1 {}; 869 pm8921_l2: l2 {}; 870 pm8921_l3: l3 {}; 871 pm8921_l4: l4 {}; 872 pm8921_l5: l5 {}; 873 pm8921_l6: l6 {}; 874 pm8921_l7: l7 {}; 875 pm8921_l8: l8 {}; 876 pm8921_l9: l9 {}; 877 pm8921_l10: l10 {}; 878 pm8921_l11: l11 {}; 879 pm8921_l12: l12 {}; 880 pm8921_l14: l14 {}; 881 pm8921_l15: l15 {}; 882 pm8921_l16: l16 {}; 883 pm8921_l17: l17 {}; 884 pm8921_l18: l18 {}; 885 pm8921_l21: l21 {}; 886 pm8921_l22: l22 {}; 887 pm8921_l23: l23 {}; 888 pm8921_l24: l24 {}; 889 pm8921_l25: l25 {}; 890 pm8921_l26: l26 {}; 891 pm8921_l27: l27 {}; 892 pm8921_l28: l28 {}; 893 pm8921_l29: l29 {}; 894 895 pm8921_lvs1: lvs1 {}; 896 pm8921_lvs2: lvs2 {}; 897 pm8921_lvs3: lvs3 {}; 898 pm8921_lvs4: lvs4 {}; 899 pm8921_lvs5: lvs5 {}; 900 pm8921_lvs6: lvs6 {}; 901 pm8921_lvs7: lvs7 {}; 902 903 pm8921_usb_switch: usb-switch {}; 904 905 pm8921_hdmi_switch: hdmi-switch { 906 bias-pull-down; 907 }; 908 909 pm8921_ncp: ncp {}; 910 }; 911 }; 912 913 usb1: usb@12500000 { 914 compatible = "qcom,ci-hdrc"; 915 reg = <0x12500000 0x200>, 916 <0x12500200 0x200>; 917 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; 919 clock-names = "core", "iface"; 920 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; 921 assigned-clock-rates = <60000000>; 922 resets = <&gcc USB_HS1_RESET>; 923 reset-names = "core"; 924 phy_type = "ulpi"; 925 ahb-burst-config = <0>; 926 phys = <&usb_hs1_phy>; 927 phy-names = "usb-phy"; 928 status = "disabled"; 929 #reset-cells = <1>; 930 931 ulpi { 932 usb_hs1_phy: phy { 933 compatible = "qcom,usb-hs-phy-apq8064", 934 "qcom,usb-hs-phy"; 935 clocks = <&sleep_clk>, <&cxo_board>; 936 clock-names = "sleep", "ref"; 937 resets = <&usb1 0>; 938 reset-names = "por"; 939 #phy-cells = <0>; 940 }; 941 }; 942 }; 943 944 usb3: usb@12520000 { 945 compatible = "qcom,ci-hdrc"; 946 reg = <0x12520000 0x200>, 947 <0x12520200 0x200>; 948 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 949 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>; 950 clock-names = "core", "iface"; 951 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>; 952 assigned-clock-rates = <60000000>; 953 resets = <&gcc USB_HS3_RESET>; 954 reset-names = "core"; 955 phy_type = "ulpi"; 956 ahb-burst-config = <0>; 957 phys = <&usb_hs3_phy>; 958 phy-names = "usb-phy"; 959 status = "disabled"; 960 #reset-cells = <1>; 961 962 ulpi { 963 usb_hs3_phy: phy { 964 compatible = "qcom,usb-hs-phy-apq8064", 965 "qcom,usb-hs-phy"; 966 #phy-cells = <0>; 967 clocks = <&sleep_clk>, <&cxo_board>; 968 clock-names = "sleep", "ref"; 969 resets = <&usb3 0>; 970 reset-names = "por"; 971 }; 972 }; 973 }; 974 975 usb4: usb@12530000 { 976 compatible = "qcom,ci-hdrc"; 977 reg = <0x12530000 0x200>, 978 <0x12530200 0x200>; 979 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>; 981 clock-names = "core", "iface"; 982 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>; 983 assigned-clock-rates = <60000000>; 984 resets = <&gcc USB_HS4_RESET>; 985 reset-names = "core"; 986 phy_type = "ulpi"; 987 ahb-burst-config = <0>; 988 phys = <&usb_hs4_phy>; 989 phy-names = "usb-phy"; 990 status = "disabled"; 991 #reset-cells = <1>; 992 993 ulpi { 994 usb_hs4_phy: phy { 995 compatible = "qcom,usb-hs-phy-apq8064", 996 "qcom,usb-hs-phy"; 997 #phy-cells = <0>; 998 clocks = <&sleep_clk>, <&cxo_board>; 999 clock-names = "sleep", "ref"; 1000 resets = <&usb4 0>; 1001 reset-names = "por"; 1002 }; 1003 }; 1004 }; 1005 1006 sata_phy0: phy@1b400000 { 1007 compatible = "qcom,apq8064-sata-phy"; 1008 status = "disabled"; 1009 reg = <0x1b400000 0x200>; 1010 reg-names = "phy_mem"; 1011 clocks = <&gcc SATA_PHY_CFG_CLK>; 1012 clock-names = "cfg"; 1013 #phy-cells = <0>; 1014 }; 1015 1016 sata0: sata@29000000 { 1017 compatible = "qcom,apq8064-ahci", "generic-ahci"; 1018 status = "disabled"; 1019 reg = <0x29000000 0x180>; 1020 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1021 1022 clocks = <&gcc SFAB_SATA_S_H_CLK>, 1023 <&gcc SATA_H_CLK>, 1024 <&gcc SATA_A_CLK>, 1025 <&gcc SATA_RXOOB_CLK>, 1026 <&gcc SATA_PMALIVE_CLK>; 1027 clock-names = "slave_iface", 1028 "iface", 1029 "bus", 1030 "rxoob", 1031 "core_pmalive"; 1032 1033 assigned-clocks = <&gcc SATA_RXOOB_CLK>, 1034 <&gcc SATA_PMALIVE_CLK>; 1035 assigned-clock-rates = <100000000>, <100000000>; 1036 1037 phys = <&sata_phy0>; 1038 phy-names = "sata-phy"; 1039 ports-implemented = <0x1>; 1040 }; 1041 1042 /* Temporary fixed regulator */ 1043 sdcc1bam: dma-controller@12402000{ 1044 compatible = "qcom,bam-v1.3.0"; 1045 reg = <0x12402000 0x8000>; 1046 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; 1047 clocks = <&gcc SDC1_H_CLK>; 1048 clock-names = "bam_clk"; 1049 #dma-cells = <1>; 1050 qcom,ee = <0>; 1051 }; 1052 1053 sdcc3bam: dma-controller@12182000{ 1054 compatible = "qcom,bam-v1.3.0"; 1055 reg = <0x12182000 0x8000>; 1056 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; 1057 clocks = <&gcc SDC3_H_CLK>; 1058 clock-names = "bam_clk"; 1059 #dma-cells = <1>; 1060 qcom,ee = <0>; 1061 }; 1062 1063 sdcc4bam: dma-controller@121c2000{ 1064 compatible = "qcom,bam-v1.3.0"; 1065 reg = <0x121c2000 0x8000>; 1066 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; 1067 clocks = <&gcc SDC4_H_CLK>; 1068 clock-names = "bam_clk"; 1069 #dma-cells = <1>; 1070 qcom,ee = <0>; 1071 }; 1072 1073 amba { 1074 compatible = "simple-bus"; 1075 #address-cells = <1>; 1076 #size-cells = <1>; 1077 ranges; 1078 sdcc1: mmc@12400000 { 1079 status = "disabled"; 1080 compatible = "arm,pl18x", "arm,primecell"; 1081 pinctrl-names = "default"; 1082 pinctrl-0 = <&sdcc1_pins>; 1083 arm,primecell-periphid = <0x00051180>; 1084 reg = <0x12400000 0x2000>; 1085 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1086 interrupt-names = "cmd_irq"; 1087 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 1088 clock-names = "mclk", "apb_pclk"; 1089 bus-width = <8>; 1090 max-frequency = <96000000>; 1091 non-removable; 1092 cap-sd-highspeed; 1093 cap-mmc-highspeed; 1094 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 1095 dma-names = "tx", "rx"; 1096 }; 1097 1098 sdcc3: mmc@12180000 { 1099 compatible = "arm,pl18x", "arm,primecell"; 1100 arm,primecell-periphid = <0x00051180>; 1101 status = "disabled"; 1102 reg = <0x12180000 0x2000>; 1103 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1104 interrupt-names = "cmd_irq"; 1105 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 1106 clock-names = "mclk", "apb_pclk"; 1107 bus-width = <4>; 1108 cap-sd-highspeed; 1109 cap-mmc-highspeed; 1110 max-frequency = <192000000>; 1111 no-1-8-v; 1112 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 1113 dma-names = "tx", "rx"; 1114 }; 1115 1116 sdcc4: mmc@121c0000 { 1117 compatible = "arm,pl18x", "arm,primecell"; 1118 arm,primecell-periphid = <0x00051180>; 1119 status = "disabled"; 1120 reg = <0x121c0000 0x2000>; 1121 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1122 interrupt-names = "cmd_irq"; 1123 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; 1124 clock-names = "mclk", "apb_pclk"; 1125 bus-width = <4>; 1126 cap-sd-highspeed; 1127 cap-mmc-highspeed; 1128 max-frequency = <48000000>; 1129 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; 1130 dma-names = "tx", "rx"; 1131 pinctrl-names = "default"; 1132 pinctrl-0 = <&sdc4_gpios>; 1133 }; 1134 }; 1135 1136 tcsr: syscon@1a400000 { 1137 compatible = "qcom,tcsr-apq8064", "syscon"; 1138 reg = <0x1a400000 0x100>; 1139 }; 1140 1141 gpu: adreno-3xx@4300000 { 1142 compatible = "qcom,adreno-320.2", "qcom,adreno"; 1143 reg = <0x04300000 0x20000>; 1144 reg-names = "kgsl_3d0_reg_memory"; 1145 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1146 interrupt-names = "kgsl_3d0_irq"; 1147 clock-names = 1148 "core", 1149 "iface", 1150 "mem", 1151 "mem_iface"; 1152 clocks = 1153 <&mmcc GFX3D_CLK>, 1154 <&mmcc GFX3D_AHB_CLK>, 1155 <&mmcc GFX3D_AXI_CLK>, 1156 <&mmcc MMSS_IMEM_AHB_CLK>; 1157 1158 iommus = <&gfx3d 0 1159 &gfx3d 1 1160 &gfx3d 2 1161 &gfx3d 3 1162 &gfx3d 4 1163 &gfx3d 5 1164 &gfx3d 6 1165 &gfx3d 7 1166 &gfx3d 8 1167 &gfx3d 9 1168 &gfx3d 10 1169 &gfx3d 11 1170 &gfx3d 12 1171 &gfx3d 13 1172 &gfx3d 14 1173 &gfx3d 15 1174 &gfx3d 16 1175 &gfx3d 17 1176 &gfx3d 18 1177 &gfx3d 19 1178 &gfx3d 20 1179 &gfx3d 21 1180 &gfx3d 22 1181 &gfx3d 23 1182 &gfx3d 24 1183 &gfx3d 25 1184 &gfx3d 26 1185 &gfx3d 27 1186 &gfx3d 28 1187 &gfx3d 29 1188 &gfx3d 30 1189 &gfx3d 31 1190 &gfx3d1 0 1191 &gfx3d1 1 1192 &gfx3d1 2 1193 &gfx3d1 3 1194 &gfx3d1 4 1195 &gfx3d1 5 1196 &gfx3d1 6 1197 &gfx3d1 7 1198 &gfx3d1 8 1199 &gfx3d1 9 1200 &gfx3d1 10 1201 &gfx3d1 11 1202 &gfx3d1 12 1203 &gfx3d1 13 1204 &gfx3d1 14 1205 &gfx3d1 15 1206 &gfx3d1 16 1207 &gfx3d1 17 1208 &gfx3d1 18 1209 &gfx3d1 19 1210 &gfx3d1 20 1211 &gfx3d1 21 1212 &gfx3d1 22 1213 &gfx3d1 23 1214 &gfx3d1 24 1215 &gfx3d1 25 1216 &gfx3d1 26 1217 &gfx3d1 27 1218 &gfx3d1 28 1219 &gfx3d1 29 1220 &gfx3d1 30 1221 &gfx3d1 31>; 1222 1223 operating-points-v2 = <&gpu_opp_table>; 1224 1225 gpu_opp_table: opp-table { 1226 compatible = "operating-points-v2"; 1227 1228 opp-320000000 { 1229 opp-hz = /bits/ 64 <450000000>; 1230 }; 1231 1232 opp-27000000 { 1233 opp-hz = /bits/ 64 <27000000>; 1234 }; 1235 }; 1236 }; 1237 1238 mmss_sfpb: syscon@5700000 { 1239 compatible = "syscon"; 1240 reg = <0x5700000 0x70>; 1241 }; 1242 1243 dsi0: dsi@4700000 { 1244 compatible = "qcom,mdss-dsi-ctrl"; 1245 label = "MDSS DSI CTRL->0"; 1246 #address-cells = <1>; 1247 #size-cells = <0>; 1248 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1249 reg = <0x04700000 0x200>; 1250 reg-names = "dsi_ctrl"; 1251 1252 clocks = <&mmcc DSI_M_AHB_CLK>, 1253 <&mmcc DSI_S_AHB_CLK>, 1254 <&mmcc AMP_AHB_CLK>, 1255 <&mmcc DSI_CLK>, 1256 <&mmcc DSI1_BYTE_CLK>, 1257 <&mmcc DSI_PIXEL_CLK>, 1258 <&mmcc DSI1_ESC_CLK>; 1259 clock-names = "iface", "bus", "core_mmss", 1260 "src", "byte", "pixel", 1261 "core"; 1262 1263 assigned-clocks = <&mmcc DSI1_BYTE_SRC>, 1264 <&mmcc DSI1_ESC_SRC>, 1265 <&mmcc DSI_SRC>, 1266 <&mmcc DSI_PIXEL_SRC>; 1267 assigned-clock-parents = <&dsi0_phy 0>, 1268 <&dsi0_phy 0>, 1269 <&dsi0_phy 1>, 1270 <&dsi0_phy 1>; 1271 syscon-sfpb = <&mmss_sfpb>; 1272 phys = <&dsi0_phy>; 1273 phy-names = "dsi"; 1274 ports { 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 1278 port@0 { 1279 reg = <0>; 1280 dsi0_in: endpoint { 1281 }; 1282 }; 1283 1284 port@1 { 1285 reg = <1>; 1286 dsi0_out: endpoint { 1287 }; 1288 }; 1289 }; 1290 }; 1291 1292 1293 dsi0_phy: dsi-phy@4700200 { 1294 compatible = "qcom,dsi-phy-28nm-8960"; 1295 #clock-cells = <1>; 1296 #phy-cells = <0>; 1297 1298 reg = <0x04700200 0x100>, 1299 <0x04700300 0x200>, 1300 <0x04700500 0x5c>; 1301 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; 1302 clock-names = "iface_clk", "ref"; 1303 clocks = <&mmcc DSI_M_AHB_CLK>, 1304 <&pxo_board>; 1305 }; 1306 1307 1308 mdp_port0: iommu@7500000 { 1309 compatible = "qcom,apq8064-iommu"; 1310 #iommu-cells = <1>; 1311 clock-names = 1312 "smmu_pclk", 1313 "iommu_clk"; 1314 clocks = 1315 <&mmcc SMMU_AHB_CLK>, 1316 <&mmcc MDP_AXI_CLK>; 1317 reg = <0x07500000 0x100000>; 1318 interrupts = 1319 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 1320 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1321 qcom,ncb = <2>; 1322 }; 1323 1324 mdp_port1: iommu@7600000 { 1325 compatible = "qcom,apq8064-iommu"; 1326 #iommu-cells = <1>; 1327 clock-names = 1328 "smmu_pclk", 1329 "iommu_clk"; 1330 clocks = 1331 <&mmcc SMMU_AHB_CLK>, 1332 <&mmcc MDP_AXI_CLK>; 1333 reg = <0x07600000 0x100000>; 1334 interrupts = 1335 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1336 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1337 qcom,ncb = <2>; 1338 }; 1339 1340 gfx3d: iommu@7c00000 { 1341 compatible = "qcom,apq8064-iommu"; 1342 #iommu-cells = <1>; 1343 clock-names = 1344 "smmu_pclk", 1345 "iommu_clk"; 1346 clocks = 1347 <&mmcc SMMU_AHB_CLK>, 1348 <&mmcc GFX3D_AXI_CLK>; 1349 reg = <0x07c00000 0x100000>; 1350 interrupts = 1351 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1353 qcom,ncb = <3>; 1354 }; 1355 1356 gfx3d1: iommu@7d00000 { 1357 compatible = "qcom,apq8064-iommu"; 1358 #iommu-cells = <1>; 1359 clock-names = 1360 "smmu_pclk", 1361 "iommu_clk"; 1362 clocks = 1363 <&mmcc SMMU_AHB_CLK>, 1364 <&mmcc GFX3D_AXI_CLK>; 1365 reg = <0x07d00000 0x100000>; 1366 interrupts = 1367 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 1369 qcom,ncb = <3>; 1370 }; 1371 1372 pcie: pci@1b500000 { 1373 compatible = "qcom,pcie-apq8064", "snps,dw-pcie"; 1374 reg = <0x1b500000 0x1000>, 1375 <0x1b502000 0x80>, 1376 <0x1b600000 0x100>, 1377 <0x0ff00000 0x100000>; 1378 reg-names = "dbi", "elbi", "parf", "config"; 1379 device_type = "pci"; 1380 linux,pci-domain = <0>; 1381 bus-range = <0x00 0xff>; 1382 num-lanes = <1>; 1383 #address-cells = <3>; 1384 #size-cells = <2>; 1385 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>, /* I/O */ 1386 <0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* mem */ 1387 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1388 interrupt-names = "msi"; 1389 #interrupt-cells = <1>; 1390 interrupt-map-mask = <0 0 0 0x7>; 1391 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1392 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1393 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1394 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1395 clocks = <&gcc PCIE_A_CLK>, 1396 <&gcc PCIE_H_CLK>, 1397 <&gcc PCIE_PHY_REF_CLK>; 1398 clock-names = "core", "iface", "phy"; 1399 resets = <&gcc PCIE_ACLK_RESET>, 1400 <&gcc PCIE_HCLK_RESET>, 1401 <&gcc PCIE_POR_RESET>, 1402 <&gcc PCIE_PCI_RESET>, 1403 <&gcc PCIE_PHY_RESET>; 1404 reset-names = "axi", "ahb", "por", "pci", "phy"; 1405 status = "disabled"; 1406 }; 1407 1408 hdmi: hdmi-tx@4a00000 { 1409 compatible = "qcom,hdmi-tx-8960"; 1410 pinctrl-names = "default"; 1411 pinctrl-0 = <&hdmi_pinctrl>; 1412 reg = <0x04a00000 0x2f0>; 1413 reg-names = "core_physical"; 1414 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1415 clocks = <&mmcc HDMI_APP_CLK>, 1416 <&mmcc HDMI_M_AHB_CLK>, 1417 <&mmcc HDMI_S_AHB_CLK>; 1418 clock-names = "core", 1419 "master_iface", 1420 "slave_iface"; 1421 1422 phys = <&hdmi_phy>; 1423 phy-names = "hdmi-phy"; 1424 1425 ports { 1426 #address-cells = <1>; 1427 #size-cells = <0>; 1428 1429 port@0 { 1430 reg = <0>; 1431 hdmi_in: endpoint { 1432 }; 1433 }; 1434 1435 port@1 { 1436 reg = <1>; 1437 hdmi_out: endpoint { 1438 }; 1439 }; 1440 }; 1441 }; 1442 1443 hdmi_phy: hdmi-phy@4a00400 { 1444 compatible = "qcom,hdmi-phy-8960"; 1445 reg = <0x4a00400 0x60>, 1446 <0x4a00500 0x100>; 1447 reg-names = "hdmi_phy", 1448 "hdmi_pll"; 1449 1450 clocks = <&mmcc HDMI_S_AHB_CLK>; 1451 clock-names = "slave_iface"; 1452 #phy-cells = <0>; 1453 }; 1454 1455 mdp: mdp@5100000 { 1456 compatible = "qcom,mdp4"; 1457 reg = <0x05100000 0xf0000>; 1458 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1459 clocks = <&mmcc MDP_CLK>, 1460 <&mmcc MDP_AHB_CLK>, 1461 <&mmcc MDP_AXI_CLK>, 1462 <&mmcc MDP_LUT_CLK>, 1463 <&mmcc HDMI_TV_CLK>, 1464 <&mmcc MDP_TV_CLK>; 1465 clock-names = "core_clk", 1466 "iface_clk", 1467 "bus_clk", 1468 "lut_clk", 1469 "hdmi_clk", 1470 "tv_clk"; 1471 1472 iommus = <&mdp_port0 0 1473 &mdp_port0 2 1474 &mdp_port1 0 1475 &mdp_port1 2>; 1476 1477 ports { 1478 #address-cells = <1>; 1479 #size-cells = <0>; 1480 1481 port@0 { 1482 reg = <0>; 1483 mdp_lvds_out: endpoint { 1484 }; 1485 }; 1486 1487 port@1 { 1488 reg = <1>; 1489 mdp_dsi1_out: endpoint { 1490 }; 1491 }; 1492 1493 port@2 { 1494 reg = <2>; 1495 mdp_dsi2_out: endpoint { 1496 }; 1497 }; 1498 1499 port@3 { 1500 reg = <3>; 1501 mdp_dtv_out: endpoint { 1502 }; 1503 }; 1504 }; 1505 }; 1506 1507 riva: riva-pil@3204000 { 1508 compatible = "qcom,riva-pil"; 1509 1510 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>; 1511 reg-names = "ccu", "dxe", "pmu"; 1512 1513 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, 1514 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>; 1515 interrupt-names = "wdog", "fatal"; 1516 1517 memory-region = <&wcnss_mem>; 1518 1519 vddcx-supply = <&pm8921_s3>; 1520 vddmx-supply = <&pm8921_l24>; 1521 vddpx-supply = <&pm8921_s4>; 1522 1523 status = "disabled"; 1524 1525 iris { 1526 compatible = "qcom,wcn3660"; 1527 1528 clocks = <&cxo_board>; 1529 clock-names = "xo"; 1530 1531 vddxo-supply = <&pm8921_l4>; 1532 vddrfa-supply = <&pm8921_s2>; 1533 vddpa-supply = <&pm8921_l10>; 1534 vdddig-supply = <&pm8921_lvs2>; 1535 }; 1536 1537 smd-edge { 1538 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>; 1539 1540 qcom,ipc = <&l2cc 8 25>; 1541 qcom,smd-edge = <6>; 1542 1543 label = "riva"; 1544 1545 wcnss { 1546 compatible = "qcom,wcnss"; 1547 qcom,smd-channels = "WCNSS_CTRL"; 1548 1549 qcom,mmio = <&riva>; 1550 1551 bluetooth { 1552 compatible = "qcom,wcnss-bt"; 1553 }; 1554 1555 wifi { 1556 compatible = "qcom,wcnss-wlan"; 1557 1558 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1560 interrupt-names = "tx", "rx"; 1561 1562 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1563 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 1564 }; 1565 }; 1566 }; 1567 }; 1568 1569 etb@1a01000 { 1570 compatible = "coresight-etb10", "arm,primecell"; 1571 reg = <0x1a01000 0x1000>; 1572 1573 clocks = <&rpmcc RPM_QDSS_CLK>; 1574 clock-names = "apb_pclk"; 1575 1576 in-ports { 1577 port { 1578 etb_in: endpoint { 1579 remote-endpoint = <&replicator_out0>; 1580 }; 1581 }; 1582 }; 1583 }; 1584 1585 tpiu@1a03000 { 1586 compatible = "arm,coresight-tpiu", "arm,primecell"; 1587 reg = <0x1a03000 0x1000>; 1588 1589 clocks = <&rpmcc RPM_QDSS_CLK>; 1590 clock-names = "apb_pclk"; 1591 1592 in-ports { 1593 port { 1594 tpiu_in: endpoint { 1595 remote-endpoint = <&replicator_out1>; 1596 }; 1597 }; 1598 }; 1599 }; 1600 1601 replicator { 1602 compatible = "arm,coresight-static-replicator"; 1603 1604 clocks = <&rpmcc RPM_QDSS_CLK>; 1605 clock-names = "apb_pclk"; 1606 1607 out-ports { 1608 #address-cells = <1>; 1609 #size-cells = <0>; 1610 1611 port@0 { 1612 reg = <0>; 1613 replicator_out0: endpoint { 1614 remote-endpoint = <&etb_in>; 1615 }; 1616 }; 1617 port@1 { 1618 reg = <1>; 1619 replicator_out1: endpoint { 1620 remote-endpoint = <&tpiu_in>; 1621 }; 1622 }; 1623 }; 1624 1625 in-ports { 1626 port { 1627 replicator_in: endpoint { 1628 remote-endpoint = <&funnel_out>; 1629 }; 1630 }; 1631 }; 1632 }; 1633 1634 funnel@1a04000 { 1635 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1636 reg = <0x1a04000 0x1000>; 1637 1638 clocks = <&rpmcc RPM_QDSS_CLK>; 1639 clock-names = "apb_pclk"; 1640 1641 in-ports { 1642 #address-cells = <1>; 1643 #size-cells = <0>; 1644 1645 /* 1646 * Not described input ports: 1647 * 2 - connected to STM component 1648 * 3 - not-connected 1649 * 6 - not-connected 1650 * 7 - not-connected 1651 */ 1652 port@0 { 1653 reg = <0>; 1654 funnel_in0: endpoint { 1655 remote-endpoint = <&etm0_out>; 1656 }; 1657 }; 1658 port@1 { 1659 reg = <1>; 1660 funnel_in1: endpoint { 1661 remote-endpoint = <&etm1_out>; 1662 }; 1663 }; 1664 port@4 { 1665 reg = <4>; 1666 funnel_in4: endpoint { 1667 remote-endpoint = <&etm2_out>; 1668 }; 1669 }; 1670 port@5 { 1671 reg = <5>; 1672 funnel_in5: endpoint { 1673 remote-endpoint = <&etm3_out>; 1674 }; 1675 }; 1676 }; 1677 1678 out-ports { 1679 port { 1680 funnel_out: endpoint { 1681 remote-endpoint = <&replicator_in>; 1682 }; 1683 }; 1684 }; 1685 }; 1686 1687 etm@1a1c000 { 1688 compatible = "arm,coresight-etm3x", "arm,primecell"; 1689 reg = <0x1a1c000 0x1000>; 1690 1691 clocks = <&rpmcc RPM_QDSS_CLK>; 1692 clock-names = "apb_pclk"; 1693 1694 cpu = <&CPU0>; 1695 1696 out-ports { 1697 port { 1698 etm0_out: endpoint { 1699 remote-endpoint = <&funnel_in0>; 1700 }; 1701 }; 1702 }; 1703 }; 1704 1705 etm@1a1d000 { 1706 compatible = "arm,coresight-etm3x", "arm,primecell"; 1707 reg = <0x1a1d000 0x1000>; 1708 1709 clocks = <&rpmcc RPM_QDSS_CLK>; 1710 clock-names = "apb_pclk"; 1711 1712 cpu = <&CPU1>; 1713 1714 out-ports { 1715 port { 1716 etm1_out: endpoint { 1717 remote-endpoint = <&funnel_in1>; 1718 }; 1719 }; 1720 }; 1721 }; 1722 1723 etm@1a1e000 { 1724 compatible = "arm,coresight-etm3x", "arm,primecell"; 1725 reg = <0x1a1e000 0x1000>; 1726 1727 clocks = <&rpmcc RPM_QDSS_CLK>; 1728 clock-names = "apb_pclk"; 1729 1730 cpu = <&CPU2>; 1731 1732 out-ports { 1733 port { 1734 etm2_out: endpoint { 1735 remote-endpoint = <&funnel_in4>; 1736 }; 1737 }; 1738 }; 1739 }; 1740 1741 etm@1a1f000 { 1742 compatible = "arm,coresight-etm3x", "arm,primecell"; 1743 reg = <0x1a1f000 0x1000>; 1744 1745 clocks = <&rpmcc RPM_QDSS_CLK>; 1746 clock-names = "apb_pclk"; 1747 1748 cpu = <&CPU3>; 1749 1750 out-ports { 1751 port { 1752 etm3_out: endpoint { 1753 remote-endpoint = <&funnel_in5>; 1754 }; 1755 }; 1756 }; 1757 }; 1758 }; 1759}; 1760#include "qcom-apq8064-pins.dtsi"