cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom-ipq4019-ap.dk04.1.dtsi (2107B)

      1// SPDX-License-Identifier: GPL-2.0
      2// Copyright (c) 2018, The Linux Foundation. All rights reserved.
      3
      4#include "qcom-ipq4019.dtsi"
      5#include <dt-bindings/input/input.h>
      6#include <dt-bindings/gpio/gpio.h>
      7
      8/ {
      9	model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
     10
     11	aliases {
     12		serial0 = &blsp1_uart1;
     13		serial1 = &blsp1_uart2;
     14	};
     15
     16	chosen {
     17		stdout-path = "serial0:115200n8";
     18	};
     19
     20	memory {
     21		device_type = "memory";
     22		reg = <0x80000000 0x10000000>; /* 256MB */
     23	};
     24
     25	soc {
     26		pinctrl@1000000 {
     27			serial_0_pins: serial0-pinmux {
     28				pins = "gpio16", "gpio17";
     29				function = "blsp_uart0";
     30				bias-disable;
     31			};
     32
     33			serial_1_pins: serial1-pinmux {
     34				pins = "gpio8", "gpio9",
     35					"gpio10", "gpio11";
     36				function = "blsp_uart1";
     37				bias-disable;
     38			};
     39
     40			spi_0_pins: spi-0-pinmux {
     41				pinmux {
     42					function = "blsp_spi0";
     43					pins = "gpio13", "gpio14", "gpio15";
     44					bias-disable;
     45				};
     46				pinmux_cs {
     47					function = "gpio";
     48					pins = "gpio12";
     49					bias-disable;
     50					output-high;
     51				};
     52			};
     53
     54			i2c_0_pins: i2c-0-pinmux {
     55				pins = "gpio20", "gpio21";
     56				function = "blsp_i2c0";
     57				bias-disable;
     58			};
     59
     60			nand_pins: nand-pins {
     61				pins = "gpio53", "gpio55", "gpio56",
     62					"gpio57", "gpio58", "gpio59",
     63					"gpio60", "gpio62", "gpio63",
     64					"gpio64", "gpio65", "gpio66",
     65					"gpio67", "gpio68", "gpio69";
     66				function = "qpic";
     67			};
     68		};
     69
     70		serial@78af000 {
     71			pinctrl-0 = <&serial_0_pins>;
     72			pinctrl-names = "default";
     73			status = "okay";
     74		};
     75
     76		serial@78b0000 {
     77			pinctrl-0 = <&serial_1_pins>;
     78			pinctrl-names = "default";
     79			status = "okay";
     80		};
     81
     82		dma-controller@7884000 {
     83			status = "okay";
     84		};
     85
     86		spi@78b5000 { /* BLSP1 QUP1 */
     87			pinctrl-0 = <&spi_0_pins>;
     88			pinctrl-names = "default";
     89			status = "okay";
     90			cs-gpios = <&tlmm 12 0>;
     91
     92			flash@0 {
     93				#address-cells = <1>;
     94				#size-cells = <1>;
     95				reg = <0>;
     96				compatible = "n25q128a11";
     97				spi-max-frequency = <24000000>;
     98			};
     99		};
    100
    101		pci@40000000 {
    102			status = "okay";
    103			perst-gpio = <&tlmm 38 0x1>;
    104		};
    105
    106		qpic-nand@79b0000 {
    107			pinctrl-0 = <&nand_pins>;
    108			pinctrl-names = "default";
    109		};
    110	};
    111};