cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom-ipq4019-ap.dk07.1-c1.dts (1208B)

      1// SPDX-License-Identifier: GPL-2.0
      2// Copyright (c) 2018, The Linux Foundation. All rights reserved.
      3
      4#include "qcom-ipq4019-ap.dk07.1.dtsi"
      5
      6/ {
      7	model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
      8	compatible = "qcom,ipq4019-ap-dk07.1-c1", "qcom,ipq4019";
      9
     10	soc {
     11		pci@40000000 {
     12			status = "okay";
     13			perst-gpio = <&tlmm 38 0x1>;
     14		};
     15
     16		spi@78b6000 {
     17			status = "okay";
     18		};
     19
     20		pinctrl@1000000 {
     21			serial_1_pins: serial1-pinmux {
     22				pins = "gpio8", "gpio9",
     23					"gpio10", "gpio11";
     24				function = "blsp_uart1";
     25				bias-disable;
     26			};
     27
     28			spi_0_pins: spi-0-pinmux {
     29				pinmux {
     30					function = "blsp_spi0";
     31					pins = "gpio13", "gpio14", "gpio15";
     32					bias-disable;
     33				};
     34				pinmux_cs {
     35					function = "gpio";
     36					pins = "gpio12";
     37					bias-disable;
     38					output-high;
     39				};
     40			};
     41		};
     42
     43		serial@78b0000 {
     44			pinctrl-0 = <&serial_1_pins>;
     45			pinctrl-names = "default";
     46			status = "okay";
     47		};
     48
     49		spi@78b5000 {
     50			pinctrl-0 = <&spi_0_pins>;
     51			pinctrl-names = "default";
     52			status = "okay";
     53			cs-gpios = <&tlmm 12 0>;
     54
     55			flash@0 {
     56				#address-cells = <1>;
     57				#size-cells = <1>;
     58				reg = <0>;
     59				compatible = "n25q128a11";
     60				spi-max-frequency = <24000000>;
     61			};
     62		};
     63	};
     64};