qcom-ipq4019.dtsi (17951B)
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/clock/qcom,gcc-ipq4019.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 model = "Qualcomm Technologies, Inc. IPQ4019"; 17 compatible = "qcom,ipq4019"; 18 interrupt-parent = <&intc>; 19 20 reserved-memory { 21 #address-cells = <0x1>; 22 #size-cells = <0x1>; 23 ranges; 24 25 smem_region: smem@87e00000 { 26 reg = <0x87e00000 0x080000>; 27 no-map; 28 }; 29 30 tz@87e80000 { 31 reg = <0x87e80000 0x180000>; 32 no-map; 33 }; 34 }; 35 36 aliases { 37 spi0 = &blsp1_spi1; 38 spi1 = &blsp1_spi2; 39 i2c0 = &blsp1_i2c3; 40 i2c1 = &blsp1_i2c4; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 enable-method = "qcom,kpss-acc-v2"; 50 next-level-cache = <&L2>; 51 qcom,acc = <&acc0>; 52 qcom,saw = <&saw0>; 53 reg = <0x0>; 54 clocks = <&gcc GCC_APPS_CLK_SRC>; 55 clock-frequency = <0>; 56 clock-latency = <256000>; 57 operating-points-v2 = <&cpu0_opp_table>; 58 }; 59 60 cpu@1 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a7"; 63 enable-method = "qcom,kpss-acc-v2"; 64 next-level-cache = <&L2>; 65 qcom,acc = <&acc1>; 66 qcom,saw = <&saw1>; 67 reg = <0x1>; 68 clocks = <&gcc GCC_APPS_CLK_SRC>; 69 clock-frequency = <0>; 70 clock-latency = <256000>; 71 operating-points-v2 = <&cpu0_opp_table>; 72 }; 73 74 cpu@2 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a7"; 77 enable-method = "qcom,kpss-acc-v2"; 78 next-level-cache = <&L2>; 79 qcom,acc = <&acc2>; 80 qcom,saw = <&saw2>; 81 reg = <0x2>; 82 clocks = <&gcc GCC_APPS_CLK_SRC>; 83 clock-frequency = <0>; 84 clock-latency = <256000>; 85 operating-points-v2 = <&cpu0_opp_table>; 86 }; 87 88 cpu@3 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a7"; 91 enable-method = "qcom,kpss-acc-v2"; 92 next-level-cache = <&L2>; 93 qcom,acc = <&acc3>; 94 qcom,saw = <&saw3>; 95 reg = <0x3>; 96 clocks = <&gcc GCC_APPS_CLK_SRC>; 97 clock-frequency = <0>; 98 clock-latency = <256000>; 99 operating-points-v2 = <&cpu0_opp_table>; 100 }; 101 102 L2: l2-cache { 103 compatible = "cache"; 104 cache-level = <2>; 105 qcom,saw = <&saw_l2>; 106 }; 107 }; 108 109 cpu0_opp_table: opp_table0 { 110 compatible = "operating-points-v2"; 111 opp-shared; 112 113 opp-48000000 { 114 opp-hz = /bits/ 64 <48000000>; 115 clock-latency-ns = <256000>; 116 }; 117 opp-200000000 { 118 opp-hz = /bits/ 64 <200000000>; 119 clock-latency-ns = <256000>; 120 }; 121 opp-500000000 { 122 opp-hz = /bits/ 64 <500000000>; 123 clock-latency-ns = <256000>; 124 }; 125 opp-716000000 { 126 opp-hz = /bits/ 64 <716000000>; 127 clock-latency-ns = <256000>; 128 }; 129 }; 130 131 memory { 132 device_type = "memory"; 133 reg = <0x0 0x0>; 134 }; 135 136 pmu { 137 compatible = "arm,cortex-a7-pmu"; 138 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 139 IRQ_TYPE_LEVEL_HIGH)>; 140 }; 141 142 clocks { 143 sleep_clk: sleep_clk { 144 compatible = "fixed-clock"; 145 clock-frequency = <32000>; 146 clock-output-names = "gcc_sleep_clk_src"; 147 #clock-cells = <0>; 148 }; 149 150 xo: xo { 151 compatible = "fixed-clock"; 152 clock-frequency = <48000000>; 153 #clock-cells = <0>; 154 }; 155 }; 156 157 firmware { 158 scm { 159 compatible = "qcom,scm-ipq4019"; 160 }; 161 }; 162 163 timer { 164 compatible = "arm,armv7-timer"; 165 interrupts = <1 2 0xf08>, 166 <1 3 0xf08>, 167 <1 4 0xf08>, 168 <1 1 0xf08>; 169 clock-frequency = <48000000>; 170 always-on; 171 }; 172 173 soc { 174 #address-cells = <1>; 175 #size-cells = <1>; 176 ranges; 177 compatible = "simple-bus"; 178 179 intc: interrupt-controller@b000000 { 180 compatible = "qcom,msm-qgic2"; 181 interrupt-controller; 182 #interrupt-cells = <3>; 183 reg = <0x0b000000 0x1000>, 184 <0x0b002000 0x1000>; 185 }; 186 187 gcc: clock-controller@1800000 { 188 compatible = "qcom,gcc-ipq4019"; 189 #clock-cells = <1>; 190 #power-domain-cells = <1>; 191 #reset-cells = <1>; 192 reg = <0x1800000 0x60000>; 193 }; 194 195 prng: rng@22000 { 196 compatible = "qcom,prng"; 197 reg = <0x22000 0x140>; 198 clocks = <&gcc GCC_PRNG_AHB_CLK>; 199 clock-names = "core"; 200 status = "disabled"; 201 }; 202 203 tlmm: pinctrl@1000000 { 204 compatible = "qcom,ipq4019-pinctrl"; 205 reg = <0x01000000 0x300000>; 206 gpio-controller; 207 gpio-ranges = <&tlmm 0 0 100>; 208 #gpio-cells = <2>; 209 interrupt-controller; 210 #interrupt-cells = <2>; 211 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 212 }; 213 214 vqmmc: regulator@1948000 { 215 compatible = "qcom,vqmmc-ipq4019-regulator"; 216 reg = <0x01948000 0x4>; 217 regulator-name = "vqmmc"; 218 regulator-min-microvolt = <1500000>; 219 regulator-max-microvolt = <3000000>; 220 regulator-always-on; 221 status = "disabled"; 222 }; 223 224 sdhci: sdhci@7824900 { 225 compatible = "qcom,sdhci-msm-v4"; 226 reg = <0x7824900 0x11c>, <0x7824000 0x800>; 227 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 228 interrupt-names = "hc_irq", "pwr_irq"; 229 bus-width = <8>; 230 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, 231 <&gcc GCC_DCD_XO_CLK>; 232 clock-names = "core", "iface", "xo"; 233 status = "disabled"; 234 }; 235 236 blsp_dma: dma-controller@7884000 { 237 compatible = "qcom,bam-v1.7.0"; 238 reg = <0x07884000 0x23000>; 239 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 241 clock-names = "bam_clk"; 242 #dma-cells = <1>; 243 qcom,ee = <0>; 244 status = "disabled"; 245 }; 246 247 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */ 248 compatible = "qcom,spi-qup-v2.2.1"; 249 reg = <0x78b5000 0x600>; 250 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 252 <&gcc GCC_BLSP1_AHB_CLK>; 253 clock-names = "core", "iface"; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 257 dma-names = "tx", "rx"; 258 status = "disabled"; 259 }; 260 261 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */ 262 compatible = "qcom,spi-qup-v2.2.1"; 263 reg = <0x78b6000 0x600>; 264 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 266 <&gcc GCC_BLSP1_AHB_CLK>; 267 clock-names = "core", "iface"; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 271 dma-names = "tx", "rx"; 272 status = "disabled"; 273 }; 274 275 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */ 276 compatible = "qcom,i2c-qup-v2.2.1"; 277 reg = <0x78b7000 0x600>; 278 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 280 <&gcc GCC_BLSP1_AHB_CLK>; 281 clock-names = "core", "iface"; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 285 dma-names = "tx", "rx"; 286 status = "disabled"; 287 }; 288 289 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */ 290 compatible = "qcom,i2c-qup-v2.2.1"; 291 reg = <0x78b8000 0x600>; 292 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 294 <&gcc GCC_BLSP1_AHB_CLK>; 295 clock-names = "core", "iface"; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 299 dma-names = "tx", "rx"; 300 status = "disabled"; 301 }; 302 303 cryptobam: dma-controller@8e04000 { 304 compatible = "qcom,bam-v1.7.0"; 305 reg = <0x08e04000 0x20000>; 306 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 308 clock-names = "bam_clk"; 309 #dma-cells = <1>; 310 qcom,ee = <1>; 311 qcom,controlled-remotely; 312 status = "disabled"; 313 }; 314 315 crypto: crypto@8e3a000 { 316 compatible = "qcom,crypto-v5.1"; 317 reg = <0x08e3a000 0x6000>; 318 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 319 <&gcc GCC_CRYPTO_AXI_CLK>, 320 <&gcc GCC_CRYPTO_CLK>; 321 clock-names = "iface", "bus", "core"; 322 dmas = <&cryptobam 2>, <&cryptobam 3>; 323 dma-names = "rx", "tx"; 324 status = "disabled"; 325 }; 326 327 acc0: clock-controller@b088000 { 328 compatible = "qcom,kpss-acc-v2"; 329 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; 330 }; 331 332 acc1: clock-controller@b098000 { 333 compatible = "qcom,kpss-acc-v2"; 334 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; 335 }; 336 337 acc2: clock-controller@b0a8000 { 338 compatible = "qcom,kpss-acc-v2"; 339 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; 340 }; 341 342 acc3: clock-controller@b0b8000 { 343 compatible = "qcom,kpss-acc-v2"; 344 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; 345 }; 346 347 saw0: regulator@b089000 { 348 compatible = "qcom,saw2"; 349 reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; 350 regulator; 351 }; 352 353 saw1: regulator@b099000 { 354 compatible = "qcom,saw2"; 355 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; 356 regulator; 357 }; 358 359 saw2: regulator@b0a9000 { 360 compatible = "qcom,saw2"; 361 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; 362 regulator; 363 }; 364 365 saw3: regulator@b0b9000 { 366 compatible = "qcom,saw2"; 367 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; 368 regulator; 369 }; 370 371 saw_l2: regulator@b012000 { 372 compatible = "qcom,saw2"; 373 reg = <0xb012000 0x1000>; 374 regulator; 375 }; 376 377 blsp1_uart1: serial@78af000 { 378 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 379 reg = <0x78af000 0x200>; 380 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 381 status = "disabled"; 382 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 383 <&gcc GCC_BLSP1_AHB_CLK>; 384 clock-names = "core", "iface"; 385 dmas = <&blsp_dma 0>, <&blsp_dma 1>; 386 dma-names = "tx", "rx"; 387 }; 388 389 blsp1_uart2: serial@78b0000 { 390 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 391 reg = <0x78b0000 0x200>; 392 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 393 status = "disabled"; 394 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 395 <&gcc GCC_BLSP1_AHB_CLK>; 396 clock-names = "core", "iface"; 397 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 398 dma-names = "tx", "rx"; 399 }; 400 401 watchdog: watchdog@b017000 { 402 compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019"; 403 reg = <0xb017000 0x40>; 404 clocks = <&sleep_clk>; 405 timeout-sec = <10>; 406 status = "disabled"; 407 }; 408 409 restart@4ab000 { 410 compatible = "qcom,pshold"; 411 reg = <0x4ab000 0x4>; 412 }; 413 414 pcie0: pci@40000000 { 415 compatible = "qcom,pcie-ipq4019", "snps,dw-pcie"; 416 reg = <0x40000000 0xf1d 417 0x40000f20 0xa8 418 0x80000 0x2000 419 0x40100000 0x1000>; 420 reg-names = "dbi", "elbi", "parf", "config"; 421 device_type = "pci"; 422 linux,pci-domain = <0>; 423 bus-range = <0x00 0xff>; 424 num-lanes = <1>; 425 #address-cells = <3>; 426 #size-cells = <2>; 427 428 ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>, 429 <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>; 430 431 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 432 interrupt-names = "msi"; 433 #interrupt-cells = <1>; 434 interrupt-map-mask = <0 0 0 0x7>; 435 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 436 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 437 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 438 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 439 clocks = <&gcc GCC_PCIE_AHB_CLK>, 440 <&gcc GCC_PCIE_AXI_M_CLK>, 441 <&gcc GCC_PCIE_AXI_S_CLK>; 442 clock-names = "aux", 443 "master_bus", 444 "slave_bus"; 445 446 resets = <&gcc PCIE_AXI_M_ARES>, 447 <&gcc PCIE_AXI_S_ARES>, 448 <&gcc PCIE_PIPE_ARES>, 449 <&gcc PCIE_AXI_M_VMIDMT_ARES>, 450 <&gcc PCIE_AXI_S_XPU_ARES>, 451 <&gcc PCIE_PARF_XPU_ARES>, 452 <&gcc PCIE_PHY_ARES>, 453 <&gcc PCIE_AXI_M_STICKY_ARES>, 454 <&gcc PCIE_PIPE_STICKY_ARES>, 455 <&gcc PCIE_PWR_ARES>, 456 <&gcc PCIE_AHB_ARES>, 457 <&gcc PCIE_PHY_AHB_ARES>; 458 reset-names = "axi_m", 459 "axi_s", 460 "pipe", 461 "axi_m_vmid", 462 "axi_s_xpu", 463 "parf", 464 "phy", 465 "axi_m_sticky", 466 "pipe_sticky", 467 "pwr", 468 "ahb", 469 "phy_ahb"; 470 471 status = "disabled"; 472 }; 473 474 qpic_bam: dma-controller@7984000 { 475 compatible = "qcom,bam-v1.7.0"; 476 reg = <0x7984000 0x1a000>; 477 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&gcc GCC_QPIC_CLK>; 479 clock-names = "bam_clk"; 480 #dma-cells = <1>; 481 qcom,ee = <0>; 482 status = "disabled"; 483 }; 484 485 nand: nand-controller@79b0000 { 486 compatible = "qcom,ipq4019-nand"; 487 reg = <0x79b0000 0x1000>; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 clocks = <&gcc GCC_QPIC_CLK>, 491 <&gcc GCC_QPIC_AHB_CLK>; 492 clock-names = "core", "aon"; 493 494 dmas = <&qpic_bam 0>, 495 <&qpic_bam 1>, 496 <&qpic_bam 2>; 497 dma-names = "tx", "rx", "cmd"; 498 status = "disabled"; 499 500 nand@0 { 501 reg = <0>; 502 503 nand-ecc-strength = <4>; 504 nand-ecc-step-size = <512>; 505 nand-bus-width = <8>; 506 }; 507 }; 508 509 wifi0: wifi@a000000 { 510 compatible = "qcom,ipq4019-wifi"; 511 reg = <0xa000000 0x200000>; 512 resets = <&gcc WIFI0_CPU_INIT_RESET>, 513 <&gcc WIFI0_RADIO_SRIF_RESET>, 514 <&gcc WIFI0_RADIO_WARM_RESET>, 515 <&gcc WIFI0_RADIO_COLD_RESET>, 516 <&gcc WIFI0_CORE_WARM_RESET>, 517 <&gcc WIFI0_CORE_COLD_RESET>; 518 reset-names = "wifi_cpu_init", "wifi_radio_srif", 519 "wifi_radio_warm", "wifi_radio_cold", 520 "wifi_core_warm", "wifi_core_cold"; 521 clocks = <&gcc GCC_WCSS2G_CLK>, 522 <&gcc GCC_WCSS2G_REF_CLK>, 523 <&gcc GCC_WCSS2G_RTC_CLK>; 524 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", 525 "wifi_wcss_rtc"; 526 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 527 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 528 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 529 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 530 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 531 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 532 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 533 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 534 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, 535 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 536 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 537 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 538 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 539 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 540 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 541 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 542 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 543 interrupt-names = "msi0", "msi1", "msi2", "msi3", 544 "msi4", "msi5", "msi6", "msi7", 545 "msi8", "msi9", "msi10", "msi11", 546 "msi12", "msi13", "msi14", "msi15", 547 "legacy"; 548 status = "disabled"; 549 }; 550 551 wifi1: wifi@a800000 { 552 compatible = "qcom,ipq4019-wifi"; 553 reg = <0xa800000 0x200000>; 554 resets = <&gcc WIFI1_CPU_INIT_RESET>, 555 <&gcc WIFI1_RADIO_SRIF_RESET>, 556 <&gcc WIFI1_RADIO_WARM_RESET>, 557 <&gcc WIFI1_RADIO_COLD_RESET>, 558 <&gcc WIFI1_CORE_WARM_RESET>, 559 <&gcc WIFI1_CORE_COLD_RESET>; 560 reset-names = "wifi_cpu_init", "wifi_radio_srif", 561 "wifi_radio_warm", "wifi_radio_cold", 562 "wifi_core_warm", "wifi_core_cold"; 563 clocks = <&gcc GCC_WCSS5G_CLK>, 564 <&gcc GCC_WCSS5G_REF_CLK>, 565 <&gcc GCC_WCSS5G_RTC_CLK>; 566 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", 567 "wifi_wcss_rtc"; 568 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 569 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 570 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 571 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 572 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 573 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 574 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 575 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 576 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>, 577 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 578 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 579 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 580 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 581 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 582 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 583 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 584 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 585 interrupt-names = "msi0", "msi1", "msi2", "msi3", 586 "msi4", "msi5", "msi6", "msi7", 587 "msi8", "msi9", "msi10", "msi11", 588 "msi12", "msi13", "msi14", "msi15", 589 "legacy"; 590 status = "disabled"; 591 }; 592 593 mdio: mdio@90000 { 594 #address-cells = <1>; 595 #size-cells = <0>; 596 compatible = "qcom,ipq4019-mdio"; 597 reg = <0x90000 0x64>; 598 status = "disabled"; 599 600 ethphy0: ethernet-phy@0 { 601 reg = <0>; 602 }; 603 604 ethphy1: ethernet-phy@1 { 605 reg = <1>; 606 }; 607 608 ethphy2: ethernet-phy@2 { 609 reg = <2>; 610 }; 611 612 ethphy3: ethernet-phy@3 { 613 reg = <3>; 614 }; 615 616 ethphy4: ethernet-phy@4 { 617 reg = <4>; 618 }; 619 }; 620 621 usb3_ss_phy: ssphy@9a000 { 622 compatible = "qcom,usb-ss-ipq4019-phy"; 623 #phy-cells = <0>; 624 reg = <0x9a000 0x800>; 625 reg-names = "phy_base"; 626 resets = <&gcc USB3_UNIPHY_PHY_ARES>; 627 reset-names = "por_rst"; 628 status = "disabled"; 629 }; 630 631 usb3_hs_phy: hsphy@a6000 { 632 compatible = "qcom,usb-hs-ipq4019-phy"; 633 #phy-cells = <0>; 634 reg = <0xa6000 0x40>; 635 reg-names = "phy_base"; 636 resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; 637 reset-names = "por_rst", "srif_rst"; 638 status = "disabled"; 639 }; 640 641 usb3: usb3@8af8800 { 642 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; 643 reg = <0x8af8800 0x100>; 644 #address-cells = <1>; 645 #size-cells = <1>; 646 clocks = <&gcc GCC_USB3_MASTER_CLK>, 647 <&gcc GCC_USB3_SLEEP_CLK>, 648 <&gcc GCC_USB3_MOCK_UTMI_CLK>; 649 clock-names = "core", "sleep", "mock_utmi"; 650 ranges; 651 status = "disabled"; 652 653 dwc3@8a00000 { 654 compatible = "snps,dwc3"; 655 reg = <0x8a00000 0xf8000>; 656 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 657 phys = <&usb3_hs_phy>, <&usb3_ss_phy>; 658 phy-names = "usb2-phy", "usb3-phy"; 659 dr_mode = "host"; 660 }; 661 }; 662 663 usb2_hs_phy: hsphy@a8000 { 664 compatible = "qcom,usb-hs-ipq4019-phy"; 665 #phy-cells = <0>; 666 reg = <0xa8000 0x40>; 667 reg-names = "phy_base"; 668 resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; 669 reset-names = "por_rst", "srif_rst"; 670 status = "disabled"; 671 }; 672 673 usb2: usb2@60f8800 { 674 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; 675 reg = <0x60f8800 0x100>; 676 #address-cells = <1>; 677 #size-cells = <1>; 678 clocks = <&gcc GCC_USB2_MASTER_CLK>, 679 <&gcc GCC_USB2_SLEEP_CLK>, 680 <&gcc GCC_USB2_MOCK_UTMI_CLK>; 681 clock-names = "master", "sleep", "mock_utmi"; 682 ranges; 683 status = "disabled"; 684 685 dwc3@6000000 { 686 compatible = "snps,dwc3"; 687 reg = <0x6000000 0xf8000>; 688 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 689 phys = <&usb2_hs_phy>; 690 phy-names = "usb2-phy"; 691 dr_mode = "host"; 692 }; 693 }; 694 }; 695};