qcom-sdx65.dtsi (9743B)
1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SDX65 SoC device tree source 4 * 5 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 6 * 7 */ 8 9#include <dt-bindings/clock/qcom,gcc-sdx65.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/soc/qcom,rpmh-rsc.h> 14 15/ { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>; 19 interrupt-parent = <&intc>; 20 21 memory { 22 device_type = "memory"; 23 reg = <0 0>; 24 }; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 clock-frequency = <76800000>; 30 clock-output-names = "xo_board"; 31 #clock-cells = <0>; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 clock-frequency = <32764>; 37 clock-output-names = "sleep_clk"; 38 #clock-cells = <0>; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 cpu0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 reg = <0x0>; 50 enable-method = "psci"; 51 }; 52 }; 53 54 psci { 55 compatible = "arm,psci-1.0"; 56 method = "smc"; 57 }; 58 59 reserved_memory: reserved-memory { 60 #address-cells = <1>; 61 #size-cells = <1>; 62 ranges; 63 64 tz_heap_mem: memory@8fcad000 { 65 no-map; 66 reg = <0x8fcad000 0x40000>; 67 }; 68 69 secdata_mem: memory@8fcfd000 { 70 no-map; 71 reg = <0x8fcfd000 0x1000>; 72 }; 73 74 hyp_mem: memory@8fd00000 { 75 no-map; 76 reg = <0x8fd00000 0x80000>; 77 }; 78 79 access_control_mem: memory@8fd80000 { 80 no-map; 81 reg = <0x8fd80000 0x80000>; 82 }; 83 84 aop_mem: memory@8fe00000 { 85 no-map; 86 reg = <0x8fe00000 0x20000>; 87 }; 88 89 smem_mem: memory@8fe20000 { 90 no-map; 91 reg = <0x8fe20000 0xc0000>; 92 }; 93 94 cmd_db: reserved-memory@8fee0000 { 95 compatible = "qcom,cmd-db"; 96 reg = <0x8fee0000 0x20000>; 97 no-map; 98 }; 99 100 tz_mem: memory@8ff00000 { 101 no-map; 102 reg = <0x8ff00000 0x100000>; 103 }; 104 105 tz_apps_mem: memory@90000000 { 106 no-map; 107 reg = <0x90000000 0x500000>; 108 }; 109 110 llcc_tcm_mem: memory@15800000 { 111 no-map; 112 reg = <0x15800000 0x800000>; 113 }; 114 }; 115 116 soc: soc { 117 #address-cells = <1>; 118 #size-cells = <1>; 119 ranges; 120 compatible = "simple-bus"; 121 122 gcc: clock-controller@100000 { 123 compatible = "qcom,gcc-sdx65"; 124 reg = <0x00100000 0x001f7400>; 125 clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; 126 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 127 #clock-cells = <1>; 128 #reset-cells = <1>; 129 }; 130 131 blsp1_uart3: serial@831000 { 132 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 133 reg = <0x00831000 0x200>; 134 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 136 clock-names = "core", "iface"; 137 status = "disabled"; 138 }; 139 140 tcsr_mutex: hwlock@1f40000 { 141 compatible = "qcom,tcsr-mutex"; 142 reg = <0x01f40000 0x40000>; 143 #hwlock-cells = <1>; 144 }; 145 146 sdhc_1: sdhci@8804000 { 147 compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; 148 reg = <0x08804000 0x1000>; 149 reg-names = "hc_mem"; 150 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 152 interrupt-names = "hc_irq", "pwr_irq"; 153 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 154 <&gcc GCC_SDCC1_AHB_CLK>; 155 clock-names = "core", "iface"; 156 status = "disabled"; 157 }; 158 159 spmi_bus: qcom,spmi@c440000 { 160 compatible = "qcom,spmi-pmic-arb"; 161 reg = <0xc440000 0xd00>, 162 <0xc600000 0x2000000>, 163 <0xe600000 0x100000>, 164 <0xe700000 0xa0000>, 165 <0xc40a000 0x26000>; 166 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 167 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 168 interrupt-names = "periph_irq"; 169 interrupt-controller; 170 #interrupt-cells = <4>; 171 #address-cells = <2>; 172 #size-cells = <0>; 173 cell-index = <0>; 174 qcom,channel = <0>; 175 qcom,ee = <0>; 176 }; 177 178 tlmm: pinctrl@f100000 { 179 compatible = "qcom,sdx65-tlmm"; 180 reg = <0xf100000 0x300000>; 181 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 182 gpio-controller; 183 #gpio-cells = <2>; 184 gpio-ranges = <&tlmm 0 0 109>; 185 interrupt-controller; 186 interrupt-parent = <&intc>; 187 #interrupt-cells = <2>; 188 }; 189 190 pdc: interrupt-controller@b210000 { 191 compatible = "qcom,sdx65-pdc", "qcom,pdc"; 192 reg = <0xb210000 0x10000>; 193 qcom,pdc-ranges = <0 147 52>, <52 266 32>; 194 #interrupt-cells = <2>; 195 interrupt-parent = <&intc>; 196 interrupt-controller; 197 }; 198 199 apps_smmu: iommu@15000000 { 200 compatible = "qcom,sdx65-smmu-500", "arm,mmu-500"; 201 reg = <0x15000000 0x40000>; 202 #iommu-cells = <2>; 203 #global-interrupts = <1>; 204 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 237 }; 238 239 intc: interrupt-controller@17800000 { 240 compatible = "qcom,msm-qgic2"; 241 interrupt-controller; 242 interrupt-parent = <&intc>; 243 #interrupt-cells = <3>; 244 reg = <0x17800000 0x1000>, 245 <0x17802000 0x1000>; 246 }; 247 248 a7pll: clock@17808000 { 249 compatible = "qcom,sdx55-a7pll"; 250 reg = <0x17808000 0x1000>; 251 clocks = <&rpmhcc RPMH_CXO_CLK>; 252 clock-names = "bi_tcxo"; 253 #clock-cells = <0>; 254 }; 255 256 apcs: mailbox@17810000 { 257 compatible = "qcom,sdx55-apcs-gcc", "syscon"; 258 reg = <0x17810000 0x2000>; 259 #mbox-cells = <1>; 260 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; 261 clock-names = "ref", "pll", "aux"; 262 #clock-cells = <0>; 263 }; 264 265 timer@17820000 { 266 #address-cells = <1>; 267 #size-cells = <1>; 268 ranges; 269 compatible = "arm,armv7-timer-mem"; 270 reg = <0x17820000 0x1000>; 271 clock-frequency = <19200000>; 272 273 frame@17821000 { 274 frame-number = <0>; 275 interrupts = <GIC_SPI 7 0x4>, 276 <GIC_SPI 6 0x4>; 277 reg = <0x17821000 0x1000>, 278 <0x17822000 0x1000>; 279 }; 280 281 frame@17823000 { 282 frame-number = <1>; 283 interrupts = <GIC_SPI 8 0x4>; 284 reg = <0x17823000 0x1000>; 285 status = "disabled"; 286 }; 287 288 frame@17824000 { 289 frame-number = <2>; 290 interrupts = <GIC_SPI 9 0x4>; 291 reg = <0x17824000 0x1000>; 292 status = "disabled"; 293 }; 294 295 frame@17825000 { 296 frame-number = <3>; 297 interrupts = <GIC_SPI 10 0x4>; 298 reg = <0x17825000 0x1000>; 299 status = "disabled"; 300 }; 301 302 frame@17826000 { 303 frame-number = <4>; 304 interrupts = <GIC_SPI 11 0x4>; 305 reg = <0x17826000 0x1000>; 306 status = "disabled"; 307 }; 308 309 frame@17827000 { 310 frame-number = <5>; 311 interrupts = <GIC_SPI 12 0x4>; 312 reg = <0x17827000 0x1000>; 313 status = "disabled"; 314 }; 315 316 frame@17828000 { 317 frame-number = <6>; 318 interrupts = <GIC_SPI 13 0x4>; 319 reg = <0x17828000 0x1000>; 320 status = "disabled"; 321 }; 322 323 frame@17829000 { 324 frame-number = <7>; 325 interrupts = <GIC_SPI 14 0x4>; 326 reg = <0x17829000 0x1000>; 327 status = "disabled"; 328 }; 329 }; 330 331 apps_rsc: rsc@17830000 { 332 label = "apps_rsc"; 333 compatible = "qcom,rpmh-rsc"; 334 reg = <0x17830000 0x10000>, 335 <0x17840000 0x10000>; 336 reg-names = "drv-0", "drv-1"; 337 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 339 qcom,tcs-offset = <0xd00>; 340 qcom,drv-id = <1>; 341 qcom,tcs-config = <ACTIVE_TCS 2>, 342 <SLEEP_TCS 2>, 343 <WAKE_TCS 2>, 344 <CONTROL_TCS 1>; 345 346 rpmhcc: clock-controller { 347 compatible = "qcom,sdx65-rpmh-clk"; 348 #clock-cells = <1>; 349 clock-names = "xo"; 350 clocks = <&xo_board>; 351 }; 352 353 rpmhpd: power-controller { 354 compatible = "qcom,sdx65-rpmhpd"; 355 #power-domain-cells = <1>; 356 operating-points-v2 = <&rpmhpd_opp_table>; 357 358 rpmhpd_opp_table: opp-table { 359 compatible = "operating-points-v2"; 360 361 rpmhpd_opp_ret: opp1 { 362 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 363 }; 364 365 rpmhpd_opp_min_svs: opp2 { 366 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 367 }; 368 369 rpmhpd_opp_low_svs: opp3 { 370 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 371 }; 372 373 rpmhpd_opp_svs: opp4 { 374 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 375 }; 376 377 rpmhpd_opp_svs_l1: opp5 { 378 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 379 }; 380 381 rpmhpd_opp_nom: opp6 { 382 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 383 }; 384 385 rpmhpd_opp_nom_l1: opp7 { 386 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 387 }; 388 389 rpmhpd_opp_nom_l2: opp8 { 390 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 391 }; 392 393 rpmhpd_opp_turbo: opp9 { 394 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 395 }; 396 397 rpmhpd_opp_turbo_l1: opp10 { 398 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 399 }; 400 }; 401 }; 402 }; 403 }; 404 405 timer { 406 compatible = "arm,armv7-timer"; 407 interrupts = <1 13 0xf08>, 408 <1 12 0xf08>, 409 <1 10 0xf08>, 410 <1 11 0xf08>; 411 clock-frequency = <19200000>; 412 }; 413};