cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

r8a7745-iwg22m.dtsi (1971B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Device Tree Source for the iWave-RZG1E-G22M SODIMM SOM
      4 *
      5 * Copyright (C) 2017 Renesas Electronics Corp.
      6 */
      7
      8#include "r8a7745.dtsi"
      9#include <dt-bindings/gpio/gpio.h>
     10
     11/ {
     12	compatible = "iwave,g22m", "renesas,r8a7745";
     13
     14	memory@40000000 {
     15		device_type = "memory";
     16		reg = <0 0x40000000 0 0x20000000>;
     17	};
     18
     19	reg_3p3v: 3p3v {
     20		compatible = "regulator-fixed";
     21		regulator-name = "3P3V";
     22		regulator-min-microvolt = <3300000>;
     23		regulator-max-microvolt = <3300000>;
     24		regulator-always-on;
     25		regulator-boot-on;
     26	};
     27};
     28
     29&cmt0 {
     30	status = "okay";
     31};
     32
     33&extal_clk {
     34	clock-frequency = <20000000>;
     35};
     36
     37&pfc {
     38	mmcif0_pins: mmc {
     39		groups = "mmc_data8", "mmc_ctrl";
     40		function = "mmc";
     41	};
     42
     43	qspi_pins: qspi {
     44		groups = "qspi_ctrl", "qspi_data2";
     45		function = "qspi";
     46	};
     47
     48	sdhi1_pins: sd1 {
     49		groups = "sdhi1_data4", "sdhi1_ctrl";
     50		function = "sdhi1";
     51		power-source = <3300>;
     52	};
     53
     54	i2c3_pins: i2c3 {
     55		groups = "i2c3_b";
     56		function = "i2c3";
     57	};
     58};
     59
     60&mmcif0 {
     61	pinctrl-0 = <&mmcif0_pins>;
     62	pinctrl-names = "default";
     63
     64	vmmc-supply = <&reg_3p3v>;
     65	bus-width = <8>;
     66	non-removable;
     67	status = "okay";
     68};
     69
     70&qspi {
     71	pinctrl-0 = <&qspi_pins>;
     72	pinctrl-names = "default";
     73
     74	status = "okay";
     75
     76	/* WARNING - This device contains the bootloader. Handle with care. */
     77	flash: flash@0 {
     78		#address-cells = <1>;
     79		#size-cells = <1>;
     80		compatible = "sst,sst25vf016b", "jedec,spi-nor";
     81		reg = <0>;
     82		spi-max-frequency = <50000000>;
     83		spi-tx-bus-width = <1>;
     84		spi-rx-bus-width = <1>;
     85		m25p,fast-read;
     86		spi-cpol;
     87		spi-cpha;
     88	};
     89};
     90
     91&rwdt {
     92	timeout-sec = <60>;
     93	status = "okay";
     94};
     95
     96&sdhi1 {
     97	pinctrl-0 = <&sdhi1_pins>;
     98	pinctrl-names = "default";
     99
    100	vmmc-supply = <&reg_3p3v>;
    101	vqmmc-supply = <&reg_3p3v>;
    102	cd-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
    103	status = "okay";
    104};
    105
    106&i2c3 {
    107	pinctrl-0 = <&i2c3_pins>;
    108	pinctrl-names = "default";
    109
    110	status = "okay";
    111	clock-frequency = <400000>;
    112
    113	rtc@68 {
    114		compatible = "ti,bq32000";
    115		reg = <0x68>;
    116	};
    117};