cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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rk3228-evb.dts (1332B)


      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2
      3/dts-v1/;
      4
      5#include "rk322x.dtsi"
      6
      7/ {
      8	model = "Rockchip RK3228 Evaluation board";
      9	compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
     10
     11	aliases {
     12		mmc0 = &emmc;
     13	};
     14
     15	memory@60000000 {
     16		device_type = "memory";
     17		reg = <0x60000000 0x40000000>;
     18	};
     19
     20	vcc_phy: vcc-phy-regulator {
     21		compatible = "regulator-fixed";
     22		enable-active-high;
     23		regulator-name = "vcc_phy";
     24		regulator-min-microvolt = <1800000>;
     25		regulator-max-microvolt = <1800000>;
     26		regulator-always-on;
     27		regulator-boot-on;
     28	};
     29};
     30
     31&emmc {
     32	cap-mmc-highspeed;
     33	mmc-ddr-1_8v;
     34	disable-wp;
     35	non-removable;
     36	status = "okay";
     37};
     38
     39&gmac {
     40	assigned-clocks = <&cru SCLK_MAC_SRC>;
     41	assigned-clock-rates = <50000000>;
     42	clock_in_out = "output";
     43	phy-supply = <&vcc_phy>;
     44	phy-mode = "rmii";
     45	phy-handle = <&phy>;
     46	status = "okay";
     47
     48	mdio {
     49		compatible = "snps,dwmac-mdio";
     50		#address-cells = <1>;
     51		#size-cells = <0>;
     52
     53		phy: ethernet-phy@0 {
     54			compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
     55			reg = <0>;
     56			clocks = <&cru SCLK_MAC_PHY>;
     57			resets = <&cru SRST_MACPHY>;
     58			phy-is-integrated;
     59		};
     60	};
     61};
     62
     63&tsadc {
     64	status = "okay";
     65
     66	rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
     67	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
     68};
     69
     70&uart2 {
     71	status = "okay";
     72};