cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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rk3288-rock2-som.dtsi (5724B)


      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2
      3#include <dt-bindings/pwm/pwm.h>
      4#include "rk3288.dtsi"
      5
      6/ {
      7	memory@0 {
      8		reg = <0x0 0x0 0x0 0x80000000>;
      9		device_type = "memory";
     10	};
     11
     12	emmc_pwrseq: emmc-pwrseq {
     13		compatible = "mmc-pwrseq-emmc";
     14		pinctrl-0 = <&emmc_reset>;
     15		pinctrl-names = "default";
     16		reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
     17	};
     18
     19	ext_gmac: external-gmac-clock {
     20		compatible = "fixed-clock";
     21		#clock-cells = <0>;
     22		clock-frequency = <125000000>;
     23		clock-output-names = "ext_gmac";
     24	};
     25
     26	vcc_flash: flash-regulator {
     27		compatible = "regulator-fixed";
     28		regulator-name = "vcc_flash";
     29		regulator-min-microvolt = <1800000>;
     30		regulator-max-microvolt = <1800000>;
     31		startup-delay-us = <150>;
     32		vin-supply = <&vcc_io>;
     33	};
     34
     35	vcc_sys: vsys-regulator {
     36		compatible = "regulator-fixed";
     37		regulator-name = "vcc_sys";
     38		regulator-min-microvolt = <5000000>;
     39		regulator-max-microvolt = <5000000>;
     40		regulator-always-on;
     41		regulator-boot-on;
     42	};
     43};
     44
     45&cpu0 {
     46	cpu0-supply = <&vdd_cpu>;
     47};
     48
     49&emmc {
     50	bus-width = <8>;
     51	cap-mmc-highspeed;
     52	disable-wp;
     53	non-removable;
     54	mmc-pwrseq = <&emmc_pwrseq>;
     55	pinctrl-names = "default";
     56	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
     57	vmmc-supply = <&vcc_io>;
     58	vqmmc-supply = <&vcc_flash>;
     59	status = "okay";
     60};
     61
     62&gmac {
     63	assigned-clocks = <&cru SCLK_MAC>;
     64	assigned-clock-parents = <&ext_gmac>;
     65	clock_in_out = "input";
     66	phy-mode = "rgmii";
     67	phy-supply = <&vccio_pmu>;
     68	pinctrl-names = "default";
     69	pinctrl-0 = <&rgmii_pins &phy_rst>;
     70	snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
     71	snps,reset-active-low;
     72	snps,reset-delays-us = <0 10000 30000>;
     73	rx_delay = <0x10>;
     74	tx_delay = <0x30>;
     75};
     76
     77&gpu {
     78	mali-supply = <&vdd_gpu>;
     79	status = "okay";
     80};
     81
     82&i2c0 {
     83	status = "okay";
     84
     85	act8846: act8846@5a {
     86		compatible = "active-semi,act8846";
     87		reg = <0x5a>;
     88		system-power-controller;
     89		inl1-supply = <&vcc_io>;
     90		inl2-supply = <&vcc_sys>;
     91		inl3-supply = <&vcc_20>;
     92		vp1-supply = <&vcc_sys>;
     93		vp2-supply = <&vcc_sys>;
     94		vp3-supply = <&vcc_sys>;
     95		vp4-supply = <&vcc_sys>;
     96
     97		regulators {
     98			vcc_ddr: REG1 {
     99				regulator-name = "VCC_DDR";
    100				regulator-min-microvolt = <1200000>;
    101				regulator-max-microvolt = <1200000>;
    102				regulator-always-on;
    103			};
    104
    105			vcc_io: vccio_codec: REG2 {
    106				regulator-name = "VCC_IO";
    107				regulator-min-microvolt = <3300000>;
    108				regulator-max-microvolt = <3300000>;
    109				regulator-always-on;
    110			};
    111
    112			vdd_log: REG3 {
    113				regulator-name = "VDD_LOG";
    114				regulator-min-microvolt = <1000000>;
    115				regulator-max-microvolt = <1000000>;
    116				regulator-always-on;
    117			};
    118
    119			vcc_20: REG4 {
    120				regulator-name = "VCC_20";
    121				regulator-min-microvolt = <2000000>;
    122				regulator-max-microvolt = <2000000>;
    123				regulator-always-on;
    124			};
    125
    126			vccio_sd: REG5 {
    127				regulator-name = "VCCIO_SD";
    128				regulator-min-microvolt = <3300000>;
    129				regulator-max-microvolt = <3300000>;
    130				regulator-always-on;
    131			};
    132
    133			vdd10_lcd: REG6 {
    134				regulator-name = "VDD10_LCD";
    135				regulator-min-microvolt = <1000000>;
    136				regulator-max-microvolt = <1000000>;
    137				regulator-always-on;
    138			};
    139
    140			vcca_codec: REG7 {
    141				regulator-name = "VCCA_CODEC";
    142				regulator-min-microvolt = <3300000>;
    143				regulator-max-microvolt = <3300000>;
    144				regulator-always-on;
    145			};
    146
    147			vcca_tp: REG8 {
    148				regulator-name = "VCCA_TP";
    149				regulator-min-microvolt = <3300000>;
    150				regulator-max-microvolt = <3300000>;
    151				regulator-always-on;
    152			};
    153
    154			vccio_pmu: REG9 {
    155				regulator-name = "VCCIO_PMU";
    156				regulator-min-microvolt = <3300000>;
    157				regulator-max-microvolt = <3300000>;
    158				regulator-always-on;
    159			};
    160
    161			vdd_10: REG10 {
    162				regulator-name = "VDD_10";
    163				regulator-min-microvolt = <1000000>;
    164				regulator-max-microvolt = <1000000>;
    165				regulator-always-on;
    166			};
    167
    168			vcc_18: REG11 {
    169				regulator-name = "VCC_18";
    170				regulator-min-microvolt = <1800000>;
    171				regulator-max-microvolt = <1800000>;
    172				regulator-always-on;
    173			};
    174
    175			vcc18_lcd: REG12 {
    176				regulator-name = "VCC18_LCD";
    177				regulator-min-microvolt = <1800000>;
    178				regulator-max-microvolt = <1800000>;
    179				regulator-always-on;
    180			};
    181		};
    182	};
    183
    184	vdd_cpu: syr827@40 {
    185		compatible = "silergy,syr827";
    186		reg = <0x40>;
    187		fcs,suspend-voltage-selector = <1>;
    188		regulator-always-on;
    189		regulator-boot-on;
    190		regulator-enable-ramp-delay = <300>;
    191		regulator-name = "vdd_cpu";
    192		regulator-min-microvolt = <850000>;
    193		regulator-max-microvolt = <1350000>;
    194		regulator-ramp-delay = <8000>;
    195		vin-supply = <&vcc_sys>;
    196	};
    197
    198	vdd_gpu: syr828@41 {
    199		compatible = "silergy,syr828";
    200		reg = <0x41>;
    201		fcs,suspend-voltage-selector = <1>;
    202		regulator-always-on;
    203		regulator-enable-ramp-delay = <300>;
    204		regulator-min-microvolt = <850000>;
    205		regulator-max-microvolt = <1350000>;
    206		regulator-name = "vdd_gpu";
    207		regulator-ramp-delay = <8000>;
    208		vin-supply = <&vcc_sys>;
    209	};
    210};
    211
    212&io_domains {
    213	status = "okay";
    214
    215	audio-supply = <&vcc_io>;
    216	bb-supply = <&vcc_io>;
    217	dvp-supply = <&vcc_18>;
    218	flash0-supply = <&vcc_flash>;
    219	flash1-supply = <&vccio_pmu>;
    220	gpio30-supply = <&vccio_pmu>;
    221	gpio1830-supply = <&vcc_io>;
    222	lcdc-supply = <&vcc_io>;
    223	sdcard-supply = <&vccio_sd>;
    224	wifi-supply = <&vcc_18>;
    225};
    226
    227&pinctrl {
    228	pcfg_output_high: pcfg-output-high {
    229		output-high;
    230	};
    231
    232	emmc {
    233		emmc_reset: emmc-reset {
    234			rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
    235		};
    236	};
    237
    238	gmac {
    239		phy_rst: phy-rst {
    240			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
    241		};
    242	};
    243};
    244
    245&saradc {
    246	vref-supply = <&vcc_18>;
    247};
    248
    249&tsadc {
    250	rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
    251	rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
    252	status = "okay";
    253};
    254
    255&vopb {
    256	status = "okay";
    257};
    258
    259&vopb_mmu {
    260	status = "okay";
    261};
    262
    263&vopl {
    264	status = "okay";
    265};
    266
    267&vopl_mmu {
    268	status = "okay";
    269};
    270
    271&wdt {
    272	status = "okay";
    273};