cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

s3c2416-pinctrl.dtsi (3181B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Samsung S3C2416 pinctrl settings
      4 *
      5 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
      6 */
      7
      8#include <dt-bindings/pinctrl/samsung.h>
      9
     10&pinctrl_0 {
     11	/*
     12	 * Pin banks
     13	 */
     14
     15	gpa: gpa-gpio-bank {
     16		gpio-controller;
     17		#gpio-cells = <2>;
     18	};
     19
     20	gpb: gpb-gpio-bank {
     21		gpio-controller;
     22		#gpio-cells = <2>;
     23	};
     24
     25	gpc: gpc-gpio-bank {
     26		gpio-controller;
     27		#gpio-cells = <2>;
     28	};
     29
     30	gpd: gpd-gpio-bank {
     31		gpio-controller;
     32		#gpio-cells = <2>;
     33	};
     34
     35	gpe: gpe-gpio-bank {
     36		gpio-controller;
     37		#gpio-cells = <2>;
     38	};
     39
     40	gpf: gpf-gpio-bank {
     41		gpio-controller;
     42		#gpio-cells = <2>;
     43		interrupt-controller;
     44		#interrupt-cells = <2>;
     45	};
     46
     47	gpg: gpg-gpio-bank {
     48		gpio-controller;
     49		#gpio-cells = <2>;
     50		interrupt-controller;
     51		#interrupt-cells = <2>;
     52	};
     53
     54	gph: gph-gpio-bank {
     55		gpio-controller;
     56		#gpio-cells = <2>;
     57	};
     58
     59	gpj: gpj-gpio-bank {
     60		gpio-controller;
     61		#gpio-cells = <2>;
     62	};
     63
     64	gpk: gpk-gpio-bank {
     65		gpio-controller;
     66		#gpio-cells = <2>;
     67	};
     68
     69	gpl: gpl-gpio-bank {
     70		gpio-controller;
     71		#gpio-cells = <2>;
     72	};
     73
     74	gpm: gpm-gpio-bank {
     75		gpio-controller;
     76		#gpio-cells = <2>;
     77	};
     78
     79	/*
     80	 * Pin groups
     81	 */
     82
     83	uart0_data: uart0-data-pins {
     84		samsung,pins = "gph-0", "gph-1";
     85		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
     86	};
     87
     88	uart0_fctl: uart0-fctl-pins {
     89		samsung,pins = "gph-8", "gph-9";
     90		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
     91	};
     92
     93	uart1_data: uart1-data-pins {
     94		samsung,pins = "gph-2", "gph-3";
     95		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
     96	};
     97
     98	uart1_fctl: uart1-fctl-pins {
     99		samsung,pins = "gph-10", "gph-11";
    100		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
    101	};
    102
    103	uart2_data: uart2-data-pins {
    104		samsung,pins = "gph-4", "gph-5";
    105		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
    106	};
    107
    108	uart2_fctl: uart2-fctl-pins {
    109		samsung,pins = "gph-6", "gph-7";
    110		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
    111	};
    112
    113	uart3_data: uart3-data-pins {
    114		samsung,pins = "gph-6", "gph-7";
    115		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
    116	};
    117
    118	extuart_clk: extuart-clk-pins {
    119		samsung,pins = "gph-12";
    120		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
    121	};
    122
    123	i2c0_bus: i2c0-bus-pins {
    124		samsung,pins = "gpe-14", "gpe-15";
    125		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
    126	};
    127
    128	spi0_bus: spi0-bus-pins {
    129		samsung,pins = "gpe-11", "gpe-12", "gpe-13";
    130		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
    131	};
    132
    133	sd0_clk: sd0-clk-pins {
    134		samsung,pins = "gpe-5";
    135		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
    136	};
    137
    138	sd0_cmd: sd0-cmd-pins {
    139		samsung,pins = "gpe-6";
    140		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
    141	};
    142
    143	sd0_bus1: sd0-bus1-pins {
    144		samsung,pins = "gpe-7";
    145		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
    146	};
    147
    148	sd0_bus4: sd0-bus4-pins {
    149		samsung,pins = "gpe-8", "gpe-9", "gpe-10";
    150		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
    151	};
    152
    153	sd1_cmd: sd1-cmd-pins {
    154		samsung,pins = "gpl-8";
    155		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
    156	};
    157
    158	sd1_clk: sd1-clk-pins {
    159		samsung,pins = "gpl-9";
    160		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
    161	};
    162
    163	sd1_bus1: sd1-bus1-pins {
    164		samsung,pins = "gpl-0";
    165		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
    166	};
    167
    168	sd1_bus4: sd1-bus4-pins {
    169		samsung,pins = "gpl-1", "gpl-2", "gpl-3";
    170		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
    171	};
    172};