cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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s3c6410-smdk6410.dts (1893B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Samsung S3C6410 based SMDK6410 board device tree source.
      4 *
      5 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
      6 *
      7 * Device tree source file for Samsung SMDK6410 board which is based on
      8 * Samsung's S3C6410 SoC.
      9 */
     10
     11/dts-v1/;
     12
     13#include <dt-bindings/gpio/gpio.h>
     14#include <dt-bindings/interrupt-controller/irq.h>
     15
     16#include "s3c6410.dtsi"
     17
     18/ {
     19	model = "Samsung SMDK6410 board based on S3C6410";
     20	compatible = "samsung,smdk6410", "samsung,s3c6410";
     21
     22	memory@50000000 {
     23		device_type = "memory";
     24		reg = <0x50000000 0x8000000>;
     25	};
     26
     27	chosen {
     28		bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1";
     29	};
     30
     31	fin_pll: oscillator-0 {
     32		compatible = "fixed-clock";
     33		clock-frequency = <12000000>;
     34		clock-output-names = "fin_pll";
     35		#clock-cells = <0>;
     36	};
     37
     38	xusbxti: oscillator-1 {
     39		compatible = "fixed-clock";
     40		clock-output-names = "xusbxti";
     41		clock-frequency = <48000000>;
     42		#clock-cells = <0>;
     43	};
     44
     45	srom-cs1-bus@18000000 {
     46		compatible = "simple-bus";
     47		#address-cells = <1>;
     48		#size-cells = <1>;
     49		reg = <0x18000000 0x8000000>;
     50		ranges;
     51
     52		ethernet@18000000 {
     53			compatible = "smsc,lan9115";
     54			reg = <0x18000000 0x10000>;
     55			interrupt-parent = <&gpn>;
     56			interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
     57			phy-mode = "mii";
     58			reg-io-width = <4>;
     59			smsc,force-internal-phy;
     60		};
     61	};
     62};
     63
     64&clocks {
     65	clocks = <&fin_pll>;
     66};
     67
     68&sdhci0 {
     69	pinctrl-names = "default";
     70	pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
     71	bus-width = <4>;
     72	status = "okay";
     73};
     74
     75&uart0 {
     76	pinctrl-names = "default";
     77	pinctrl-0 = <&uart0_data>, <&uart0_fctl>;
     78	status = "okay";
     79};
     80
     81&uart1 {
     82	pinctrl-names = "default";
     83	pinctrl-0 = <&uart1_data>;
     84	status = "okay";
     85};
     86
     87&uart2 {
     88	pinctrl-names = "default";
     89	pinctrl-0 = <&uart2_data>;
     90	status = "okay";
     91};
     92
     93&uart3 {
     94	pinctrl-names = "default";
     95	pinctrl-0 = <&uart3_data>;
     96	status = "okay";
     97};