cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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s5pv210-torbreck.dts (1915B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Samsung's S5PV210 SoC device tree source
      4 *
      5 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
      6 *
      7 * Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
      8 * Tomasz Figa <t.figa@samsung.com>
      9 *
     10 * Board device tree source for Torbreck board.
     11 *
     12 * NOTE: This file is completely based on original board file for mach-torbreck
     13 * available in Linux 3.15 and intends to provide equivalent level of hardware
     14 * support. Due to lack of hardware, _no_ testing has been performed.
     15 */
     16
     17/dts-v1/;
     18#include <dt-bindings/input/input.h>
     19#include "s5pv210.dtsi"
     20
     21/ {
     22	model = "aESOP Torbreck based on S5PV210";
     23	compatible = "aesop,torbreck", "samsung,s5pv210";
     24
     25	chosen {
     26		bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk";
     27	};
     28
     29	memory@20000000 {
     30		device_type = "memory";
     31		reg = <0x20000000 0x20000000>;
     32	};
     33
     34	pmic_ap_clk: clock-0 {
     35		/* Workaround for missing PMIC and its clock */
     36		compatible = "fixed-clock";
     37		#clock-cells = <0>;
     38		clock-frequency = <32768>;
     39	};
     40};
     41
     42&xusbxti {
     43	clock-frequency = <24000000>;
     44};
     45
     46&uart0 {
     47	status = "okay";
     48};
     49
     50&uart1 {
     51	status = "okay";
     52};
     53
     54&uart2 {
     55	status = "okay";
     56};
     57
     58&uart3 {
     59	status = "okay";
     60};
     61
     62&rtc {
     63	status = "okay";
     64	clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>;
     65	clock-names = "rtc", "rtc_src";
     66};
     67
     68&sdhci0 {
     69	bus-width = <4>;
     70	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>;
     71	pinctrl-names = "default";
     72	status = "okay";
     73};
     74
     75&sdhci1 {
     76	bus-width = <4>;
     77	pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus1 &sd1_bus4>;
     78	pinctrl-names = "default";
     79	status = "okay";
     80};
     81
     82&sdhci2 {
     83	bus-width = <4>;
     84	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
     85	pinctrl-names = "default";
     86	status = "okay";
     87};
     88
     89&sdhci3 {
     90	bus-width = <4>;
     91	pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_cd &sd3_bus1 &sd3_bus4>;
     92	pinctrl-names = "default";
     93	status = "okay";
     94};
     95
     96&i2s0 {
     97	status = "okay";
     98};