sama5d4.dtsi (48451B)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC 4 * 5 * Copyright (C) 2014 Atmel, 6 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com> 7 */ 8 9#include <dt-bindings/clock/at91.h> 10#include <dt-bindings/dma/at91.h> 11#include <dt-bindings/pinctrl/at91.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/gpio/gpio.h> 14 15/ { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 model = "Atmel SAMA5D4 family SoC"; 19 compatible = "atmel,sama5d4"; 20 interrupt-parent = <&aic>; 21 22 aliases { 23 serial0 = &usart3; 24 serial1 = &usart4; 25 serial2 = &usart2; 26 serial3 = &usart0; 27 serial4 = &usart1; 28 serial5 = &uart0; 29 serial6 = &uart1; 30 gpio0 = &pioA; 31 gpio1 = &pioB; 32 gpio2 = &pioC; 33 gpio3 = &pioD; 34 gpio4 = &pioE; 35 pwm0 = &pwm0; 36 ssc0 = &ssc0; 37 ssc1 = &ssc1; 38 tcb0 = &tcb0; 39 tcb1 = &tcb1; 40 i2c0 = &i2c0; 41 i2c1 = &i2c1; 42 i2c2 = &i2c2; 43 }; 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 cpu@0 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a5"; 51 reg = <0>; 52 next-level-cache = <&L2>; 53 }; 54 }; 55 56 memory@20000000 { 57 device_type = "memory"; 58 reg = <0x20000000 0x20000000>; 59 }; 60 61 clocks { 62 slow_xtal: slow_xtal { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 clock-frequency = <0>; 66 }; 67 68 main_xtal: main_xtal { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <0>; 72 }; 73 74 adc_op_clk: adc_op_clk{ 75 compatible = "fixed-clock"; 76 #clock-cells = <0>; 77 clock-frequency = <1000000>; 78 }; 79 }; 80 81 ns_sram: sram@210000 { 82 compatible = "mmio-sram"; 83 reg = <0x00210000 0x10000>; 84 #address-cells = <1>; 85 #size-cells = <1>; 86 ranges = <0 0x00210000 0x10000>; 87 }; 88 89 ahb { 90 compatible = "simple-bus"; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 ranges; 94 95 nfc_sram: sram@100000 { 96 compatible = "mmio-sram"; 97 no-memory-wc; 98 reg = <0x100000 0x2400>; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 ranges = <0 0x100000 0x2400>; 102 }; 103 104 vdec0: vdec@300000 { 105 compatible = "microchip,sama5d4-vdec"; 106 reg = <0x00300000 0x100000>; 107 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; 108 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 109 }; 110 111 usb0: gadget@400000 { 112 compatible = "atmel,sama5d3-udc"; 113 reg = <0x00400000 0x100000 114 0xfc02c000 0x4000>; 115 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>; 116 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 117 clock-names = "pclk", "hclk"; 118 status = "disabled"; 119 }; 120 121 usb1: ohci@500000 { 122 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 123 reg = <0x00500000 0x100000>; 124 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; 125 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 6>; 126 clock-names = "ohci_clk", "hclk", "uhpck"; 127 status = "disabled"; 128 }; 129 130 usb2: ehci@600000 { 131 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 132 reg = <0x00600000 0x100000>; 133 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; 134 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 46>; 135 clock-names = "usb_clk", "ehci_clk"; 136 status = "disabled"; 137 }; 138 139 L2: cache-controller@a00000 { 140 compatible = "arm,pl310-cache"; 141 reg = <0x00a00000 0x1000>; 142 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>; 143 cache-unified; 144 cache-level = <2>; 145 }; 146 147 ebi: ebi@10000000 { 148 compatible = "atmel,sama5d3-ebi"; 149 #address-cells = <2>; 150 #size-cells = <1>; 151 atmel,smc = <&hsmc>; 152 reg = <0x10000000 0x10000000 153 0x60000000 0x28000000>; 154 ranges = <0x0 0x0 0x10000000 0x10000000 155 0x1 0x0 0x60000000 0x10000000 156 0x2 0x0 0x70000000 0x10000000 157 0x3 0x0 0x80000000 0x8000000>; 158 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 159 status = "disabled"; 160 161 nand_controller: nand-controller { 162 compatible = "atmel,sama5d3-nand-controller"; 163 atmel,nfc-sram = <&nfc_sram>; 164 atmel,nfc-io = <&nfc_io>; 165 ecc-engine = <&pmecc>; 166 #address-cells = <2>; 167 #size-cells = <1>; 168 ranges; 169 status = "disabled"; 170 }; 171 }; 172 173 nfc_io: nfc-io@90000000 { 174 compatible = "atmel,sama5d3-nfc-io", "syscon"; 175 reg = <0x90000000 0x8000000>; 176 }; 177 178 apb { 179 compatible = "simple-bus"; 180 #address-cells = <1>; 181 #size-cells = <1>; 182 ranges; 183 184 hlcdc: hlcdc@f0000000 { 185 compatible = "atmel,sama5d4-hlcdc"; 186 reg = <0xf0000000 0x4000>; 187 interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>; 188 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; 189 clock-names = "periph_clk","sys_clk", "slow_clk"; 190 status = "disabled"; 191 192 hlcdc-display-controller { 193 compatible = "atmel,hlcdc-display-controller"; 194 #address-cells = <1>; 195 #size-cells = <0>; 196 197 port@0 { 198 #address-cells = <1>; 199 #size-cells = <0>; 200 reg = <0>; 201 }; 202 }; 203 204 hlcdc_pwm: hlcdc-pwm { 205 compatible = "atmel,hlcdc-pwm"; 206 pinctrl-names = "default"; 207 pinctrl-0 = <&pinctrl_lcd_pwm>; 208 #pwm-cells = <3>; 209 }; 210 }; 211 212 dma1: dma-controller@f0004000 { 213 compatible = "atmel,sama5d4-dma"; 214 reg = <0xf0004000 0x200>; 215 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>; 216 #dma-cells = <1>; 217 clocks = <&pmc PMC_TYPE_PERIPHERAL 50>; 218 clock-names = "dma_clk"; 219 }; 220 221 isi: isi@f0008000 { 222 compatible = "atmel,at91sam9g45-isi"; 223 reg = <0xf0008000 0x4000>; 224 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>; 225 pinctrl-names = "default"; 226 pinctrl-0 = <&pinctrl_isi_data_0_7>; 227 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; 228 clock-names = "isi_clk"; 229 status = "disabled"; 230 port { 231 #address-cells = <1>; 232 #size-cells = <0>; 233 }; 234 }; 235 236 ramc0: ramc@f0010000 { 237 compatible = "atmel,sama5d3-ddramc"; 238 reg = <0xf0010000 0x200>; 239 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 16>; 240 clock-names = "ddrck", "mpddr"; 241 }; 242 243 dma0: dma-controller@f0014000 { 244 compatible = "atmel,sama5d4-dma"; 245 reg = <0xf0014000 0x200>; 246 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>; 247 #dma-cells = <1>; 248 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 249 clock-names = "dma_clk"; 250 }; 251 252 pmc: pmc@f0018000 { 253 compatible = "atmel,sama5d4-pmc", "syscon"; 254 reg = <0xf0018000 0x120>; 255 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 256 #clock-cells = <2>; 257 clocks = <&clk32k>, <&main_xtal>; 258 clock-names = "slow_clk", "main_xtal"; 259 }; 260 261 mmc0: mmc@f8000000 { 262 compatible = "atmel,hsmci"; 263 reg = <0xf8000000 0x600>; 264 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; 265 dmas = <&dma1 266 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 267 | AT91_XDMAC_DT_PERID(0))>; 268 dma-names = "rxtx"; 269 pinctrl-names = "default"; 270 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>; 271 status = "disabled"; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; 275 clock-names = "mci_clk"; 276 }; 277 278 uart0: serial@f8004000 { 279 compatible = "atmel,at91sam9260-usart"; 280 reg = <0xf8004000 0x100>; 281 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>; 282 dmas = <&dma0 283 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 284 | AT91_XDMAC_DT_PERID(22))>, 285 <&dma0 286 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 287 | AT91_XDMAC_DT_PERID(23))>; 288 dma-names = "tx", "rx"; 289 pinctrl-names = "default"; 290 pinctrl-0 = <&pinctrl_uart0>; 291 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 292 clock-names = "usart"; 293 status = "disabled"; 294 }; 295 296 ssc0: ssc@f8008000 { 297 compatible = "atmel,at91sam9g45-ssc"; 298 reg = <0xf8008000 0x4000>; 299 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 302 dmas = <&dma1 303 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 304 | AT91_XDMAC_DT_PERID(26))>, 305 <&dma1 306 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 307 | AT91_XDMAC_DT_PERID(27))>; 308 dma-names = "tx", "rx"; 309 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; 310 clock-names = "pclk"; 311 status = "disabled"; 312 }; 313 314 pwm0: pwm@f800c000 { 315 compatible = "atmel,sama5d3-pwm"; 316 reg = <0xf800c000 0x300>; 317 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; 318 #pwm-cells = <3>; 319 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 320 status = "disabled"; 321 }; 322 323 spi0: spi@f8010000 { 324 #address-cells = <1>; 325 #size-cells = <0>; 326 compatible = "atmel,at91rm9200-spi"; 327 reg = <0xf8010000 0x100>; 328 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>; 329 dmas = <&dma1 330 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 331 | AT91_XDMAC_DT_PERID(10))>, 332 <&dma1 333 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 334 | AT91_XDMAC_DT_PERID(11))>; 335 dma-names = "tx", "rx"; 336 pinctrl-names = "default"; 337 pinctrl-0 = <&pinctrl_spi0>; 338 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 339 clock-names = "spi_clk"; 340 status = "disabled"; 341 }; 342 343 i2c0: i2c@f8014000 { 344 compatible = "atmel,sama5d4-i2c"; 345 reg = <0xf8014000 0x4000>; 346 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>; 347 dmas = <&dma1 348 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 349 | AT91_XDMAC_DT_PERID(2))>, 350 <&dma1 351 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 352 | AT91_XDMAC_DT_PERID(3))>; 353 dma-names = "tx", "rx"; 354 pinctrl-names = "default", "gpio"; 355 pinctrl-0 = <&pinctrl_i2c0>; 356 pinctrl-1 = <&pinctrl_i2c0_gpio>; 357 sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; 358 scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 362 status = "disabled"; 363 }; 364 365 i2c1: i2c@f8018000 { 366 compatible = "atmel,sama5d4-i2c"; 367 reg = <0xf8018000 0x4000>; 368 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>; 369 dmas = <&dma0 370 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 371 | AT91_XDMAC_DT_PERID(4))>, 372 <&dma0 373 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 374 | AT91_XDMAC_DT_PERID(5))>; 375 dma-names = "tx", "rx"; 376 pinctrl-names = "default", "gpio"; 377 pinctrl-0 = <&pinctrl_i2c1>; 378 pinctrl-1 = <&pinctrl_i2c1_gpio>; 379 sda-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; 380 scl-gpios = <&pioE 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 384 status = "disabled"; 385 }; 386 387 tcb0: timer@f801c000 { 388 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 reg = <0xf801c000 0x100>; 392 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; 393 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>, <&clk32k>; 394 clock-names = "t0_clk", "slow_clk"; 395 }; 396 397 macb0: ethernet@f8020000 { 398 compatible = "atmel,sama5d4-gem"; 399 reg = <0xf8020000 0x100>; 400 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>; 401 pinctrl-names = "default"; 402 pinctrl-0 = <&pinctrl_macb0_rmii>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_PERIPHERAL 54>; 406 clock-names = "hclk", "pclk"; 407 status = "disabled"; 408 }; 409 410 i2c2: i2c@f8024000 { 411 compatible = "atmel,sama5d4-i2c"; 412 reg = <0xf8024000 0x4000>; 413 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>; 414 dmas = <&dma1 415 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 416 | AT91_XDMAC_DT_PERID(6))>, 417 <&dma1 418 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 419 | AT91_XDMAC_DT_PERID(7))>; 420 dma-names = "tx", "rx"; 421 pinctrl-names = "default", "gpio"; 422 pinctrl-0 = <&pinctrl_i2c2>; 423 pinctrl-1 = <&pinctrl_i2c2_gpio>; 424 sda-gpios = <&pioB 29 GPIO_ACTIVE_HIGH>; 425 scl-gpios = <&pioB 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 429 status = "disabled"; 430 }; 431 432 sfr: sfr@f8028000 { 433 compatible = "atmel,sama5d4-sfr", "syscon"; 434 reg = <0xf8028000 0x60>; 435 }; 436 437 usart0: serial@f802c000 { 438 compatible = "atmel,at91sam9260-usart"; 439 reg = <0xf802c000 0x100>; 440 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; 441 dmas = <&dma0 442 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 443 | AT91_XDMAC_DT_PERID(36))>, 444 <&dma0 445 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 446 | AT91_XDMAC_DT_PERID(37))>; 447 dma-names = "tx", "rx"; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>; 450 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 451 clock-names = "usart"; 452 status = "disabled"; 453 }; 454 455 usart1: serial@f8030000 { 456 compatible = "atmel,at91sam9260-usart"; 457 reg = <0xf8030000 0x100>; 458 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 459 dmas = <&dma0 460 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 461 | AT91_XDMAC_DT_PERID(38))>, 462 <&dma0 463 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 464 | AT91_XDMAC_DT_PERID(39))>; 465 dma-names = "tx", "rx"; 466 pinctrl-names = "default"; 467 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>; 468 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 469 clock-names = "usart"; 470 status = "disabled"; 471 }; 472 473 mmc1: mmc@fc000000 { 474 compatible = "atmel,hsmci"; 475 reg = <0xfc000000 0x600>; 476 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; 477 dmas = <&dma1 478 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 479 | AT91_XDMAC_DT_PERID(1))>; 480 dma-names = "rxtx"; 481 pinctrl-names = "default"; 482 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; 483 status = "disabled"; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; 487 clock-names = "mci_clk"; 488 }; 489 490 uart1: serial@fc004000 { 491 compatible = "atmel,at91sam9260-usart"; 492 reg = <0xfc004000 0x100>; 493 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; 494 dmas = <&dma0 495 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 496 | AT91_XDMAC_DT_PERID(24))>, 497 <&dma0 498 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 499 | AT91_XDMAC_DT_PERID(25))>; 500 dma-names = "tx", "rx"; 501 pinctrl-names = "default"; 502 pinctrl-0 = <&pinctrl_uart1>; 503 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 504 clock-names = "usart"; 505 status = "disabled"; 506 }; 507 508 usart2: serial@fc008000 { 509 compatible = "atmel,at91sam9260-usart"; 510 reg = <0xfc008000 0x100>; 511 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; 512 dmas = <&dma1 513 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 514 | AT91_XDMAC_DT_PERID(16))>, 515 <&dma1 516 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 517 | AT91_XDMAC_DT_PERID(17))>; 518 dma-names = "tx", "rx"; 519 pinctrl-names = "default"; 520 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>; 521 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 522 clock-names = "usart"; 523 status = "disabled"; 524 }; 525 526 usart3: serial@fc00c000 { 527 compatible = "atmel,at91sam9260-usart"; 528 reg = <0xfc00c000 0x100>; 529 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>; 530 dmas = <&dma1 531 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 532 | AT91_XDMAC_DT_PERID(18))>, 533 <&dma1 534 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 535 | AT91_XDMAC_DT_PERID(19))>; 536 dma-names = "tx", "rx"; 537 pinctrl-names = "default"; 538 pinctrl-0 = <&pinctrl_usart3>; 539 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 540 clock-names = "usart"; 541 status = "disabled"; 542 }; 543 544 usart4: serial@fc010000 { 545 compatible = "atmel,at91sam9260-usart"; 546 reg = <0xfc010000 0x100>; 547 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>; 548 dmas = <&dma1 549 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 550 | AT91_XDMAC_DT_PERID(20))>, 551 <&dma1 552 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 553 | AT91_XDMAC_DT_PERID(21))>; 554 dma-names = "tx", "rx"; 555 pinctrl-names = "default"; 556 pinctrl-0 = <&pinctrl_usart4>; 557 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>; 558 clock-names = "usart"; 559 status = "disabled"; 560 }; 561 562 ssc1: ssc@fc014000 { 563 compatible = "atmel,at91sam9g45-ssc"; 564 reg = <0xfc014000 0x4000>; 565 interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>; 566 pinctrl-names = "default"; 567 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 568 dmas = <&dma1 569 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 570 | AT91_XDMAC_DT_PERID(28))>, 571 <&dma1 572 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 573 | AT91_XDMAC_DT_PERID(29))>; 574 dma-names = "tx", "rx"; 575 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; 576 clock-names = "pclk"; 577 status = "disabled"; 578 }; 579 580 spi1: spi@fc018000 { 581 #address-cells = <1>; 582 #size-cells = <0>; 583 compatible = "atmel,at91rm9200-spi"; 584 reg = <0xfc018000 0x100>; 585 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>; 586 dmas = <&dma1 587 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 588 | AT91_XDMAC_DT_PERID(12))>, 589 <&dma1 590 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 591 | AT91_XDMAC_DT_PERID(13))>; 592 dma-names = "tx", "rx"; 593 pinctrl-names = "default"; 594 pinctrl-0 = <&pinctrl_spi1>; 595 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 596 clock-names = "spi_clk"; 597 status = "disabled"; 598 }; 599 600 spi2: spi@fc01c000 { 601 #address-cells = <1>; 602 #size-cells = <0>; 603 compatible = "atmel,at91rm9200-spi"; 604 reg = <0xfc01c000 0x100>; 605 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>; 606 dmas = <&dma0 607 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 608 | AT91_XDMAC_DT_PERID(14))>, 609 <&dma0 610 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 611 | AT91_XDMAC_DT_PERID(15))>; 612 dma-names = "tx", "rx"; 613 pinctrl-names = "default"; 614 pinctrl-0 = <&pinctrl_spi2>; 615 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 616 clock-names = "spi_clk"; 617 status = "disabled"; 618 }; 619 620 tcb1: timer@fc020000 { 621 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 reg = <0xfc020000 0x100>; 625 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; 626 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&clk32k>; 627 clock-names = "t0_clk", "slow_clk"; 628 }; 629 630 tcb2: timer@fc024000 { 631 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 reg = <0xfc024000 0x100>; 635 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; 636 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&clk32k>; 637 clock-names = "t0_clk", "slow_clk"; 638 }; 639 640 macb1: ethernet@fc028000 { 641 compatible = "atmel,sama5d4-gem"; 642 reg = <0xfc028000 0x100>; 643 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>; 644 pinctrl-names = "default"; 645 pinctrl-0 = <&pinctrl_macb1_rmii>; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_PERIPHERAL 55>; 649 clock-names = "hclk", "pclk"; 650 status = "disabled"; 651 }; 652 653 trng@fc030000 { 654 compatible = "atmel,at91sam9g45-trng"; 655 reg = <0xfc030000 0x100>; 656 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>; 657 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; 658 }; 659 660 adc0: adc@fc034000 { 661 compatible = "atmel,at91sam9x5-adc"; 662 reg = <0xfc034000 0x100>; 663 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>; 664 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>, 665 <&adc_op_clk>; 666 clock-names = "adc_clk", "adc_op_clk"; 667 atmel,adc-channels-used = <0x01f>; 668 atmel,adc-startup-time = <40>; 669 atmel,adc-use-external-triggers; 670 atmel,adc-vref = <3000>; 671 atmel,adc-sample-hold-time = <11>; 672 atmel,adc-ts-pressure-threshold = <10000>; 673 status = "disabled"; 674 }; 675 676 aes: crypto@fc044000 { 677 compatible = "atmel,at91sam9g46-aes"; 678 reg = <0xfc044000 0x100>; 679 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 680 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 681 | AT91_XDMAC_DT_PERID(41))>, 682 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 683 | AT91_XDMAC_DT_PERID(40))>; 684 dma-names = "tx", "rx"; 685 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; 686 clock-names = "aes_clk"; 687 }; 688 689 tdes: crpyto@fc04c000 { 690 compatible = "atmel,at91sam9g46-tdes"; 691 reg = <0xfc04c000 0x100>; 692 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>; 693 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 694 | AT91_XDMAC_DT_PERID(42))>, 695 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 696 | AT91_XDMAC_DT_PERID(43))>; 697 dma-names = "tx", "rx"; 698 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 699 clock-names = "tdes_clk"; 700 }; 701 702 sha: crypto@fc050000 { 703 compatible = "atmel,at91sam9g46-sha"; 704 reg = <0xfc050000 0x100>; 705 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>; 706 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 707 | AT91_XDMAC_DT_PERID(44))>; 708 dma-names = "tx"; 709 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 710 clock-names = "sha_clk"; 711 }; 712 713 hsmc: smc@fc05c000 { 714 compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; 715 reg = <0xfc05c000 0x1000>; 716 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>; 717 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 718 #address-cells = <1>; 719 #size-cells = <1>; 720 ranges; 721 722 pmecc: ecc-engine@ffffc070 { 723 compatible = "atmel,sama5d4-pmecc"; 724 reg = <0xfc05c070 0x490>, 725 <0xfc05c500 0x100>; 726 }; 727 }; 728 729 reset_controller: rstc@fc068600 { 730 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; 731 reg = <0xfc068600 0x10>; 732 clocks = <&clk32k>; 733 }; 734 735 shutdown_controller: shdwc@fc068610 { 736 compatible = "atmel,at91sam9x5-shdwc"; 737 reg = <0xfc068610 0x10>; 738 clocks = <&clk32k>; 739 }; 740 741 pit: timer@fc068630 { 742 compatible = "atmel,at91sam9260-pit"; 743 reg = <0xfc068630 0x10>; 744 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 745 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 746 }; 747 748 watchdog: watchdog@fc068640 { 749 compatible = "atmel,sama5d4-wdt"; 750 reg = <0xfc068640 0x10>; 751 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; 752 clocks = <&clk32k>; 753 status = "disabled"; 754 }; 755 756 clk32k: sckc@fc068650 { 757 compatible = "atmel,sama5d4-sckc"; 758 reg = <0xfc068650 0x4>; 759 #clock-cells = <0>; 760 clocks = <&slow_xtal>; 761 }; 762 763 rtc@fc0686b0 { 764 compatible = "atmel,sama5d4-rtc"; 765 reg = <0xfc0686b0 0x30>; 766 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 767 clocks = <&clk32k>; 768 }; 769 770 dbgu: serial@fc069000 { 771 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 772 reg = <0xfc069000 0x200>; 773 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>; 774 pinctrl-names = "default"; 775 pinctrl-0 = <&pinctrl_dbgu>; 776 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; 777 clock-names = "usart"; 778 status = "disabled"; 779 }; 780 781 782 pinctrl: pinctrl@fc06a000 { 783 #address-cells = <1>; 784 #size-cells = <1>; 785 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; 786 ranges = <0xfc068000 0xfc068000 0x100 787 0xfc06a000 0xfc06a000 0x4000>; 788 /* WARNING: revisit as pin spec has changed */ 789 atmel,mux-mask = < 790 /* A B C */ 791 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */ 792 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */ 793 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */ 794 0xb003ff00 0x8002a800 0x00000000 /* pioD */ 795 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */ 796 >; 797 798 pioA: gpio@fc06a000 { 799 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 800 reg = <0xfc06a000 0x100>; 801 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>; 802 #gpio-cells = <2>; 803 gpio-controller; 804 interrupt-controller; 805 #interrupt-cells = <2>; 806 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 807 }; 808 809 pioB: gpio@fc06b000 { 810 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 811 reg = <0xfc06b000 0x100>; 812 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>; 813 #gpio-cells = <2>; 814 gpio-controller; 815 interrupt-controller; 816 #interrupt-cells = <2>; 817 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 818 }; 819 820 pioC: gpio@fc06c000 { 821 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 822 reg = <0xfc06c000 0x100>; 823 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>; 824 #gpio-cells = <2>; 825 gpio-controller; 826 interrupt-controller; 827 #interrupt-cells = <2>; 828 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; 829 }; 830 831 pioD: gpio@fc068000 { 832 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 833 reg = <0xfc068000 0x100>; 834 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; 835 #gpio-cells = <2>; 836 gpio-controller; 837 interrupt-controller; 838 #interrupt-cells = <2>; 839 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 840 }; 841 842 pioE: gpio@fc06d000 { 843 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 844 reg = <0xfc06d000 0x100>; 845 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>; 846 #gpio-cells = <2>; 847 gpio-controller; 848 interrupt-controller; 849 #interrupt-cells = <2>; 850 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; 851 }; 852 853 /* pinctrl pin settings */ 854 adc0 { 855 pinctrl_adc0_adtrg: adc0_adtrg { 856 atmel,pins = 857 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */ 858 }; 859 pinctrl_adc0_ad0: adc0_ad0 { 860 atmel,pins = 861 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; 862 }; 863 pinctrl_adc0_ad1: adc0_ad1 { 864 atmel,pins = 865 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; 866 }; 867 pinctrl_adc0_ad2: adc0_ad2 { 868 atmel,pins = 869 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; 870 }; 871 pinctrl_adc0_ad3: adc0_ad3 { 872 atmel,pins = 873 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; 874 }; 875 pinctrl_adc0_ad4: adc0_ad4 { 876 atmel,pins = 877 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; 878 }; 879 }; 880 881 dbgu { 882 pinctrl_dbgu: dbgu-0 { 883 atmel,pins = 884 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* conflicts with D14 and TDI */ 885 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with D15 and TDO */ 886 }; 887 }; 888 889 ebi { 890 pinctrl_ebi_addr: ebi-addr-0 { 891 atmel,pins = 892 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE 893 AT91_PIOE 1 AT91_PERIPH_A AT91_PINCTRL_NONE 894 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE 895 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE 896 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE 897 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE 898 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE 899 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE 900 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE 901 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE 902 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE 903 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE 904 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE 905 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE 906 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE 907 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE 908 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE 909 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE 910 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE 911 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE 912 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE 913 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE 914 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE 915 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE 916 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE 917 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; 918 }; 919 920 pinctrl_ebi_nand_addr: ebi-addr-1 { 921 atmel,pins = 922 <AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE 923 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; 924 }; 925 926 pinctrl_ebi_cs0: ebi-cs0-0 { 927 atmel,pins = 928 <AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; 929 }; 930 931 pinctrl_ebi_cs1: ebi-cs1-0 { 932 atmel,pins = 933 <AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; 934 }; 935 936 pinctrl_ebi_cs2: ebi-cs2-0 { 937 atmel,pins = 938 <AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; 939 }; 940 941 pinctrl_ebi_cs3: ebi-cs3-0 { 942 atmel,pins = 943 <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; 944 }; 945 946 pinctrl_ebi_data_0_7: ebi-data-lsb-0 { 947 atmel,pins = 948 <AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE 949 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE 950 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE 951 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE 952 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE 953 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE 954 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE 955 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; 956 }; 957 958 pinctrl_ebi_data_8_15: ebi-data-msb-0 { 959 atmel,pins = 960 <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE 961 AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE 962 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE 963 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE 964 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE 965 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE 966 AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE 967 AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; 968 }; 969 970 pinctrl_ebi_nandrdy: ebi-nandrdy-0 { 971 atmel,pins = 972 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; 973 }; 974 975 pinctrl_ebi_nrd_nandoe: ebi-nrd-nandoe-0 { 976 atmel,pins = 977 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; 978 }; 979 980 pinctrl_ebi_nwait: ebi-nwait-0 { 981 atmel,pins = 982 <AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; 983 }; 984 985 pinctrl_ebi_nwe_nandwe: ebi-nwe-nandwe-0 { 986 atmel,pins = 987 <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; 988 }; 989 990 pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 { 991 atmel,pins = 992 <AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; 993 }; 994 }; 995 996 i2c0 { 997 pinctrl_i2c0: i2c0-0 { 998 atmel,pins = 999 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE 1000 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1001 }; 1002 1003 pinctrl_i2c0_gpio: i2c0-gpio { 1004 atmel,pins = 1005 <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE 1006 AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 1007 }; 1008 }; 1009 1010 i2c1 { 1011 pinctrl_i2c1: i2c1-0 { 1012 atmel,pins = 1013 <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */ 1014 AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */ 1015 }; 1016 1017 pinctrl_i2c1_gpio: i2c1-gpio { 1018 atmel,pins = 1019 <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE 1020 AT91_PIOE 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 1021 }; 1022 }; 1023 1024 i2c2 { 1025 pinctrl_i2c2: i2c2-0 { 1026 atmel,pins = 1027 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */ 1028 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */ 1029 }; 1030 1031 pinctrl_i2c2_gpio: i2c2-gpio { 1032 atmel,pins = 1033 <AT91_PIOB 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE 1034 AT91_PIOB 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; 1035 }; 1036 }; 1037 1038 isi { 1039 pinctrl_isi_data_0_7: isi-0-data-0-7 { 1040 atmel,pins = 1041 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D0 */ 1042 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D1 */ 1043 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D2 */ 1044 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D3 */ 1045 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D4 */ 1046 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D5 */ 1047 AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D6 */ 1048 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D7 */ 1049 AT91_PIOB 1 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_PCK, conflict with G0_RXCK */ 1050 AT91_PIOB 3 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_VSYNC */ 1051 AT91_PIOB 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */ 1052 }; 1053 pinctrl_isi_data_8_9: isi-0-data-8-9 { 1054 atmel,pins = 1055 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */ 1056 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */ 1057 }; 1058 pinctrl_isi_data_10_11: isi-0-data-10-11 { 1059 atmel,pins = 1060 <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */ 1061 AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */ 1062 }; 1063 }; 1064 1065 lcd { 1066 pinctrl_lcd_base: lcd-base-0 { 1067 atmel,pins = 1068 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */ 1069 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */ 1070 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */ 1071 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */ 1072 }; 1073 pinctrl_lcd_pwm: lcd-pwm-0 { 1074 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */ 1075 }; 1076 pinctrl_lcd_rgb444: lcd-rgb-0 { 1077 atmel,pins = 1078 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ 1079 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ 1080 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 1081 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 1082 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 1083 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 1084 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 1085 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 1086 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ 1087 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ 1088 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 1089 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */ 1090 }; 1091 pinctrl_lcd_rgb565: lcd-rgb-1 { 1092 atmel,pins = 1093 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ 1094 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ 1095 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 1096 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 1097 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 1098 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 1099 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 1100 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 1101 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ 1102 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ 1103 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 1104 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ 1105 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ 1106 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ 1107 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ 1108 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */ 1109 }; 1110 pinctrl_lcd_rgb666: lcd-rgb-2 { 1111 atmel,pins = 1112 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 1113 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 1114 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 1115 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 1116 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 1117 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 1118 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 1119 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ 1120 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ 1121 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ 1122 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ 1123 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ 1124 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ 1125 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ 1126 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ 1127 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ 1128 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ 1129 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ 1130 }; 1131 pinctrl_lcd_rgb777: lcd-rgb-3 { 1132 atmel,pins = 1133 /* LCDDAT0 conflicts with TMS */ 1134 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ 1135 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 1136 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 1137 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 1138 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 1139 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 1140 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 1141 /* LCDDAT8 conflicts with TCK */ 1142 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ 1143 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 1144 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ 1145 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ 1146 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ 1147 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ 1148 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ 1149 /* LCDDAT16 conflicts with NTRST */ 1150 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */ 1151 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ 1152 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ 1153 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ 1154 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ 1155 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ 1156 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ 1157 }; 1158 pinctrl_lcd_rgb888: lcd-rgb-4 { 1159 atmel,pins = 1160 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ 1161 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ 1162 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 1163 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 1164 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 1165 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 1166 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 1167 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 1168 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ 1169 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ 1170 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 1171 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ 1172 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ 1173 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ 1174 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ 1175 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ 1176 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */ 1177 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */ 1178 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ 1179 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ 1180 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ 1181 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ 1182 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ 1183 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ 1184 }; 1185 }; 1186 1187 macb0 { 1188 pinctrl_macb0_rmii: macb0_rmii-0 { 1189 atmel,pins = 1190 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */ 1191 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */ 1192 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */ 1193 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */ 1194 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */ 1195 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */ 1196 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */ 1197 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */ 1198 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */ 1199 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */ 1200 >; 1201 }; 1202 }; 1203 1204 macb1 { 1205 pinctrl_macb1_rmii: macb1_rmii-0 { 1206 atmel,pins = 1207 <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX0 */ 1208 AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX1 */ 1209 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX0 */ 1210 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX1 */ 1211 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXDV */ 1212 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXER */ 1213 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXEN */ 1214 AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXCK */ 1215 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDC */ 1216 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDIO */ 1217 >; 1218 }; 1219 }; 1220 1221 mmc0 { 1222 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { 1223 atmel,pins = 1224 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */ 1225 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDA, conflict with NAND_D0 */ 1226 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA0, conflict with NAND_D1 */ 1227 >; 1228 }; 1229 pinctrl_mmc0_dat1_3: mmc0_dat1_3 { 1230 atmel,pins = 1231 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA1, conflict with NAND_D2 */ 1232 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA2, conflict with NAND_D3 */ 1233 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA3, conflict with NAND_D4 */ 1234 >; 1235 }; 1236 pinctrl_mmc0_dat4_7: mmc0_dat4_7 { 1237 atmel,pins = 1238 <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA4, conflict with NAND_D5 */ 1239 AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA5, conflict with NAND_D6 */ 1240 AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA6, conflict with NAND_D7 */ 1241 AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA7, conflict with NAND_OE */ 1242 >; 1243 }; 1244 }; 1245 1246 mmc1 { 1247 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { 1248 atmel,pins = 1249 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */ 1250 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */ 1251 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */ 1252 >; 1253 }; 1254 pinctrl_mmc1_dat1_3: mmc1_dat1_3 { 1255 atmel,pins = 1256 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */ 1257 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */ 1258 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */ 1259 >; 1260 }; 1261 }; 1262 1263 nand0 { 1264 pinctrl_nand: nand-0 { 1265 atmel,pins = 1266 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */ 1267 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */ 1268 1269 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */ 1270 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */ 1271 1272 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */ 1273 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */ 1274 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */ 1275 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */ 1276 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */ 1277 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */ 1278 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */ 1279 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */ 1280 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */ 1281 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */ 1282 }; 1283 }; 1284 1285 spi0 { 1286 pinctrl_spi0: spi0-0 { 1287 atmel,pins = 1288 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */ 1289 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */ 1290 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */ 1291 >; 1292 }; 1293 }; 1294 1295 ssc0 { 1296 pinctrl_ssc0_tx: ssc0_tx { 1297 atmel,pins = 1298 <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK0 */ 1299 AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF0 */ 1300 AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */ 1301 }; 1302 1303 pinctrl_ssc0_rx: ssc0_rx { 1304 atmel,pins = 1305 <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK0 */ 1306 AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF0 */ 1307 AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */ 1308 }; 1309 }; 1310 1311 ssc1 { 1312 pinctrl_ssc1_tx: ssc1_tx { 1313 atmel,pins = 1314 <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK1 */ 1315 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF1 */ 1316 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */ 1317 }; 1318 1319 pinctrl_ssc1_rx: ssc1_rx { 1320 atmel,pins = 1321 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK1 */ 1322 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF1 */ 1323 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */ 1324 }; 1325 }; 1326 1327 spi1 { 1328 pinctrl_spi1: spi1-0 { 1329 atmel,pins = 1330 <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MISO */ 1331 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MOSI */ 1332 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_SPCK */ 1333 >; 1334 }; 1335 }; 1336 1337 spi2 { 1338 pinctrl_spi2: spi2-0 { 1339 atmel,pins = 1340 <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MISO conflicts with RTS0 */ 1341 AT91_PIOD 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MOSI conflicts with TXD0 */ 1342 AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_SPCK conflicts with RTS1 */ 1343 >; 1344 }; 1345 }; 1346 1347 uart0 { 1348 pinctrl_uart0: uart0-0 { 1349 atmel,pins = 1350 <AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */ 1351 AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */ 1352 >; 1353 }; 1354 }; 1355 1356 uart1 { 1357 pinctrl_uart1: uart1-0 { 1358 atmel,pins = 1359 <AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* RXD */ 1360 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE /* TXD */ 1361 >; 1362 }; 1363 }; 1364 1365 usart0 { 1366 pinctrl_usart0: usart0-0 { 1367 atmel,pins = 1368 <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */ 1369 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */ 1370 >; 1371 }; 1372 pinctrl_usart0_rts: usart0_rts-0 { 1373 atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1374 }; 1375 pinctrl_usart0_cts: usart0_cts-0 { 1376 atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1377 }; 1378 }; 1379 1380 usart1 { 1381 pinctrl_usart1: usart1-0 { 1382 atmel,pins = 1383 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */ 1384 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */ 1385 >; 1386 }; 1387 pinctrl_usart1_rts: usart1_rts-0 { 1388 atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1389 }; 1390 pinctrl_usart1_cts: usart1_cts-0 { 1391 atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1392 }; 1393 }; 1394 1395 usart2 { 1396 pinctrl_usart2: usart2-0 { 1397 atmel,pins = 1398 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD - conflicts with G0_CRS, ISI_HSYNC */ 1399 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD - conflicts with G0_COL, PCK2 */ 1400 >; 1401 }; 1402 pinctrl_usart2_rts: usart2_rts-0 { 1403 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */ 1404 }; 1405 pinctrl_usart2_cts: usart2_cts-0 { 1406 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */ 1407 }; 1408 }; 1409 1410 usart3 { 1411 pinctrl_usart3: usart3-0 { 1412 atmel,pins = 1413 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */ 1414 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */ 1415 >; 1416 }; 1417 }; 1418 1419 usart4 { 1420 pinctrl_usart4: usart4-0 { 1421 atmel,pins = 1422 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */ 1423 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */ 1424 >; 1425 }; 1426 pinctrl_usart4_rts: usart4_rts-0 { 1427 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */ 1428 }; 1429 pinctrl_usart4_cts: usart4_cts-0 { 1430 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */ 1431 }; 1432 }; 1433 }; 1434 1435 aic: interrupt-controller@fc06e000 { 1436 #interrupt-cells = <3>; 1437 compatible = "atmel,sama5d4-aic"; 1438 interrupt-controller; 1439 reg = <0xfc06e000 0x200>; 1440 atmel,external-irqs = <56>; 1441 }; 1442 }; 1443 }; 1444};