sama7g5.dtsi (26266B)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC 4 * 5 * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries 6 * 7 * Author: Eugen Hristev <eugen.hristev@microchip.com> 8 * Author: Claudiu Beznea <claudiu.beznea@microchip.com> 9 * 10 */ 11 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/clock/at91.h> 15#include <dt-bindings/dma/at91.h> 16#include <dt-bindings/gpio/gpio.h> 17 18/ { 19 model = "Microchip SAMA7G5 family SoC"; 20 compatible = "microchip,sama7g5"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 interrupt-parent = <&gic>; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a7"; 32 reg = <0x0>; 33 clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; 34 clock-names = "cpu"; 35 operating-points-v2 = <&cpu_opp_table>; 36 }; 37 }; 38 39 cpu_opp_table: opp-table { 40 compatible = "operating-points-v2"; 41 42 opp-90000000 { 43 opp-hz = /bits/ 64 <90000000>; 44 opp-microvolt = <1050000 1050000 1225000>; 45 clock-latency-ns = <320000>; 46 }; 47 48 opp-250000000 { 49 opp-hz = /bits/ 64 <250000000>; 50 opp-microvolt = <1050000 1050000 1225000>; 51 clock-latency-ns = <320000>; 52 }; 53 54 opp-600000000 { 55 opp-hz = /bits/ 64 <600000000>; 56 opp-microvolt = <1050000 1050000 1225000>; 57 clock-latency-ns = <320000>; 58 opp-suspend; 59 }; 60 61 opp-800000000 { 62 opp-hz = /bits/ 64 <800000000>; 63 opp-microvolt = <1150000 1125000 1225000>; 64 clock-latency-ns = <320000>; 65 }; 66 67 opp-1000000002 { 68 opp-hz = /bits/ 64 <1000000002>; 69 opp-microvolt = <1250000 1225000 1300000>; 70 clock-latency-ns = <320000>; 71 }; 72 }; 73 74 clocks { 75 slow_xtal: slow_xtal { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 }; 79 80 main_xtal: main_xtal { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 }; 84 85 usb_clk: usb_clk { 86 compatible = "fixed-clock"; 87 #clock-cells = <0>; 88 clock-frequency = <48000000>; 89 }; 90 }; 91 92 vddout25: fixed-regulator-vddout25 { 93 compatible = "regulator-fixed"; 94 95 regulator-name = "VDDOUT25"; 96 regulator-min-microvolt = <2500000>; 97 regulator-max-microvolt = <2500000>; 98 regulator-boot-on; 99 status = "disabled"; 100 }; 101 102 ns_sram: sram@100000 { 103 compatible = "mmio-sram"; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 reg = <0x100000 0x20000>; 107 ranges; 108 }; 109 110 soc { 111 compatible = "simple-bus"; 112 #address-cells = <1>; 113 #size-cells = <1>; 114 ranges; 115 116 nfc_sram: sram@600000 { 117 compatible = "mmio-sram"; 118 no-memory-wc; 119 reg = <0x00600000 0x2400>; 120 #address-cells = <1>; 121 #size-cells = <1>; 122 ranges = <0 0x00600000 0x2400>; 123 }; 124 125 nfc_io: nfc-io@10000000 { 126 compatible = "atmel,sama5d3-nfc-io", "syscon"; 127 reg = <0x10000000 0x8000000>; 128 }; 129 130 ebi: ebi@40000000 { 131 compatible = "atmel,sama5d3-ebi"; 132 #address-cells = <2>; 133 #size-cells = <1>; 134 atmel,smc = <&hsmc>; 135 reg = <0x40000000 0x20000000>; 136 ranges = <0x0 0x0 0x40000000 0x8000000 137 0x1 0x0 0x48000000 0x8000000 138 0x2 0x0 0x50000000 0x8000000 139 0x3 0x0 0x58000000 0x8000000>; 140 clocks = <&pmc PMC_TYPE_CORE PMC_MCK1>; 141 status = "disabled"; 142 143 nand_controller: nand-controller { 144 compatible = "atmel,sama5d3-nand-controller"; 145 atmel,nfc-sram = <&nfc_sram>; 146 atmel,nfc-io = <&nfc_io>; 147 ecc-engine = <&pmecc>; 148 #address-cells = <2>; 149 #size-cells = <1>; 150 ranges; 151 status = "disabled"; 152 }; 153 }; 154 155 securam: securam@e0000000 { 156 compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram"; 157 reg = <0xe0000000 0x4000>; 158 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 159 #address-cells = <1>; 160 #size-cells = <1>; 161 ranges = <0 0xe0000000 0x4000>; 162 no-memory-wc; 163 }; 164 165 secumod: secumod@e0004000 { 166 compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon"; 167 reg = <0xe0004000 0x4000>; 168 gpio-controller; 169 #gpio-cells = <2>; 170 }; 171 172 sfrbu: sfr@e0008000 { 173 compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; 174 reg = <0xe0008000 0x20>; 175 }; 176 177 pioA: pinctrl@e0014000 { 178 compatible = "microchip,sama7g5-pinctrl"; 179 reg = <0xe0014000 0x800>; 180 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 185 interrupt-controller; 186 #interrupt-cells = <2>; 187 gpio-controller; 188 #gpio-cells = <2>; 189 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 190 }; 191 192 pmc: pmc@e0018000 { 193 compatible = "microchip,sama7g5-pmc", "syscon"; 194 reg = <0xe0018000 0x200>; 195 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 196 #clock-cells = <2>; 197 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 198 clock-names = "td_slck", "md_slck", "main_xtal"; 199 }; 200 201 shdwc: shdwc@e001d010 { 202 compatible = "microchip,sama7g5-shdwc", "syscon"; 203 reg = <0xe001d010 0x10>; 204 clocks = <&clk32k 0>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 atmel,wakeup-rtc-timer; 208 atmel,wakeup-rtt-timer; 209 status = "disabled"; 210 }; 211 212 rtt: rtc@e001d020 { 213 compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; 214 reg = <0xe001d020 0x30>; 215 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&clk32k 0>; 217 }; 218 219 clk32k: clock-controller@e001d050 { 220 compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc"; 221 reg = <0xe001d050 0x4>; 222 clocks = <&slow_xtal>; 223 #clock-cells = <1>; 224 }; 225 226 gpbr: gpbr@e001d060 { 227 compatible = "microchip,sama7g5-gpbr", "syscon"; 228 reg = <0xe001d060 0x48>; 229 }; 230 231 rtc: rtc@e001d0a8 { 232 compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc"; 233 reg = <0xe001d0a8 0x30>; 234 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&clk32k 1>; 236 }; 237 238 ps_wdt: watchdog@e001d180 { 239 compatible = "microchip,sama7g5-wdt"; 240 reg = <0xe001d180 0x24>; 241 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&clk32k 0>; 243 }; 244 245 chipid@e0020000 { 246 compatible = "microchip,sama7g5-chipid"; 247 reg = <0xe0020000 0x8>; 248 }; 249 250 tcb1: timer@e0800000 { 251 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 reg = <0xe0800000 0x100>; 255 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>; 257 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 258 }; 259 260 hsmc: hsmc@e0808000 { 261 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; 262 reg = <0xe0808000 0x1000>; 263 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 265 #address-cells = <1>; 266 #size-cells = <1>; 267 ranges; 268 269 pmecc: ecc-engine@e0808070 { 270 compatible = "atmel,sama5d2-pmecc"; 271 reg = <0xe0808070 0x490>, 272 <0xe0808500 0x200>; 273 }; 274 }; 275 276 qspi0: spi@e080c000 { 277 compatible = "microchip,sama7g5-ospi"; 278 reg = <0xe080c000 0x400>, <0x20000000 0x10000000>; 279 reg-names = "qspi_base", "qspi_mmap"; 280 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 281 dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>, 282 <&dma0 AT91_XDMAC_DT_PERID(40)>; 283 dma-names = "tx", "rx"; 284 clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>; 285 clock-names = "pclk", "gclk"; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 status = "disabled"; 289 }; 290 291 qspi1: spi@e0810000 { 292 compatible = "microchip,sama7g5-qspi"; 293 reg = <0xe0810000 0x400>, <0x30000000 0x10000000>; 294 reg-names = "qspi_base", "qspi_mmap"; 295 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 296 dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>, 297 <&dma0 AT91_XDMAC_DT_PERID(42)>; 298 dma-names = "tx", "rx"; 299 clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>; 300 clock-names = "pclk", "gclk"; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 status = "disabled"; 304 }; 305 306 can0: can@e0828000 { 307 compatible = "bosch,m_can"; 308 reg = <0xe0828000 0x100>, <0x100000 0x7800>; 309 reg-names = "m_can", "message_ram"; 310 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH 311 GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 312 interrupt-names = "int0", "int1"; 313 clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; 314 clock-names = "hclk", "cclk"; 315 assigned-clocks = <&pmc PMC_TYPE_GCK 61>; 316 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 317 assigned-clock-rates = <40000000>; 318 bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; 319 status = "disabled"; 320 }; 321 322 can1: can@e082c000 { 323 compatible = "bosch,m_can"; 324 reg = <0xe082c000 0x100>, <0x100000 0xbc00>; 325 reg-names = "m_can", "message_ram"; 326 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 327 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 328 interrupt-names = "int0", "int1"; 329 clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; 330 clock-names = "hclk", "cclk"; 331 assigned-clocks = <&pmc PMC_TYPE_GCK 62>; 332 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 333 assigned-clock-rates = <40000000>; 334 bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; 335 status = "disabled"; 336 }; 337 338 can2: can@e0830000 { 339 compatible = "bosch,m_can"; 340 reg = <0xe0830000 0x100>, <0x100000 0x10000>; 341 reg-names = "m_can", "message_ram"; 342 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH 343 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 344 interrupt-names = "int0", "int1"; 345 clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>; 346 clock-names = "hclk", "cclk"; 347 assigned-clocks = <&pmc PMC_TYPE_GCK 63>; 348 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 349 assigned-clock-rates = <40000000>; 350 bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>; 351 status = "disabled"; 352 }; 353 354 can3: can@e0834000 { 355 compatible = "bosch,m_can"; 356 reg = <0xe0834000 0x100>, <0x110000 0x4400>; 357 reg-names = "m_can", "message_ram"; 358 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 359 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 360 interrupt-names = "int0", "int1"; 361 clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>; 362 clock-names = "hclk", "cclk"; 363 assigned-clocks = <&pmc PMC_TYPE_GCK 64>; 364 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 365 assigned-clock-rates = <40000000>; 366 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 367 status = "disabled"; 368 }; 369 370 can4: can@e0838000 { 371 compatible = "bosch,m_can"; 372 reg = <0xe0838000 0x100>, <0x110000 0x8800>; 373 reg-names = "m_can", "message_ram"; 374 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 375 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 376 interrupt-names = "int0", "int1"; 377 clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>; 378 clock-names = "hclk", "cclk"; 379 assigned-clocks = <&pmc PMC_TYPE_GCK 65>; 380 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 381 assigned-clock-rates = <40000000>; 382 bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>; 383 status = "disabled"; 384 }; 385 386 can5: can@e083c000 { 387 compatible = "bosch,m_can"; 388 reg = <0xe083c000 0x100>, <0x110000 0xcc00>; 389 reg-names = "m_can", "message_ram"; 390 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 391 GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 392 interrupt-names = "int0", "int1"; 393 clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; 394 clock-names = "hclk", "cclk"; 395 assigned-clocks = <&pmc PMC_TYPE_GCK 66>; 396 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 397 assigned-clock-rates = <40000000>; 398 bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>; 399 status = "disabled"; 400 }; 401 402 adc: adc@e1000000 { 403 compatible = "microchip,sama7g5-adc"; 404 reg = <0xe1000000 0x200>; 405 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&pmc PMC_TYPE_GCK 26>; 407 assigned-clocks = <&pmc PMC_TYPE_GCK 26>; 408 assigned-clock-rates = <100000000>; 409 clock-names = "adc_clk"; 410 dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>; 411 dma-names = "rx"; 412 atmel,min-sample-rate-hz = <200000>; 413 atmel,max-sample-rate-hz = <20000000>; 414 atmel,startup-time-ms = <4>; 415 status = "disabled"; 416 }; 417 418 sdmmc0: mmc@e1204000 { 419 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 420 reg = <0xe1204000 0x4000>; 421 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>; 423 clock-names = "hclock", "multclk"; 424 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 425 assigned-clocks = <&pmc PMC_TYPE_GCK 80>; 426 assigned-clock-rates = <200000000>; 427 microchip,sdcal-inverted; 428 status = "disabled"; 429 }; 430 431 sdmmc1: mmc@e1208000 { 432 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 433 reg = <0xe1208000 0x4000>; 434 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>; 436 clock-names = "hclock", "multclk"; 437 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 438 assigned-clocks = <&pmc PMC_TYPE_GCK 81>; 439 assigned-clock-rates = <200000000>; 440 microchip,sdcal-inverted; 441 status = "disabled"; 442 }; 443 444 sdmmc2: mmc@e120c000 { 445 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 446 reg = <0xe120c000 0x4000>; 447 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>; 449 clock-names = "hclock", "multclk"; 450 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 451 assigned-clocks = <&pmc PMC_TYPE_GCK 82>; 452 assigned-clock-rates = <200000000>; 453 microchip,sdcal-inverted; 454 status = "disabled"; 455 }; 456 457 pwm: pwm@e1604000 { 458 compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; 459 reg = <0xe1604000 0x4000>; 460 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 461 #pwm-cells = <3>; 462 clocks = <&pmc PMC_TYPE_PERIPHERAL 77>; 463 status = "disabled"; 464 }; 465 466 pdmc0: sound@e1608000 { 467 compatible = "microchip,sama7g5-pdmc"; 468 reg = <0xe1608000 0x1000>; 469 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 470 #sound-dai-cells = <0>; 471 dmas = <&dma0 AT91_XDMAC_DT_PERID(37)>; 472 dma-names = "rx"; 473 clocks = <&pmc PMC_TYPE_PERIPHERAL 68>, <&pmc PMC_TYPE_GCK 68>; 474 clock-names = "pclk", "gclk"; 475 status = "disabled"; 476 }; 477 478 pdmc1: sound@e160c000 { 479 compatible = "microchip,sama7g5-pdmc"; 480 reg = <0xe160c000 0x1000>; 481 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 482 #sound-dai-cells = <0>; 483 dmas = <&dma0 AT91_XDMAC_DT_PERID(38)>; 484 dma-names = "rx"; 485 clocks = <&pmc PMC_TYPE_PERIPHERAL 69>, <&pmc PMC_TYPE_GCK 69>; 486 clock-names = "pclk", "gclk"; 487 status = "disabled"; 488 }; 489 490 spdifrx: spdifrx@e1614000 { 491 #sound-dai-cells = <0>; 492 compatible = "microchip,sama7g5-spdifrx"; 493 reg = <0xe1614000 0x4000>; 494 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 495 dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>; 496 dma-names = "rx"; 497 clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>; 498 clock-names = "pclk", "gclk"; 499 status = "disabled"; 500 }; 501 502 spdiftx: spdiftx@e1618000 { 503 #sound-dai-cells = <0>; 504 compatible = "microchip,sama7g5-spdiftx"; 505 reg = <0xe1618000 0x4000>; 506 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 507 dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>; 508 dma-names = "tx"; 509 clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>; 510 clock-names = "pclk", "gclk"; 511 }; 512 513 i2s0: i2s@e161c000 { 514 compatible = "microchip,sama7g5-i2smcc"; 515 #sound-dai-cells = <0>; 516 reg = <0xe161c000 0x4000>; 517 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 518 dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>; 519 dma-names = "tx", "rx"; 520 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; 521 clock-names = "pclk", "gclk"; 522 status = "disabled"; 523 }; 524 525 i2s1: i2s@e1620000 { 526 compatible = "microchip,sama7g5-i2smcc"; 527 #sound-dai-cells = <0>; 528 reg = <0xe1620000 0x4000>; 529 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 530 dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>; 531 dma-names = "tx", "rx"; 532 clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; 533 clock-names = "pclk", "gclk"; 534 status = "disabled"; 535 }; 536 537 eic: interrupt-controller@e1628000 { 538 compatible = "microchip,sama7g5-eic"; 539 reg = <0xe1628000 0xec>; 540 interrupt-parent = <&gic>; 541 interrupt-controller; 542 #interrupt-cells = <2>; 543 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 546 clock-names = "pclk"; 547 status = "disabled"; 548 }; 549 550 pit64b0: timer@e1800000 { 551 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; 552 reg = <0xe1800000 0x4000>; 553 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>; 555 clock-names = "pclk", "gclk"; 556 }; 557 558 pit64b1: timer@e1804000 { 559 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; 560 reg = <0xe1804000 0x4000>; 561 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>; 563 clock-names = "pclk", "gclk"; 564 }; 565 566 aes: crypto@e1810000 { 567 compatible = "atmel,at91sam9g46-aes"; 568 reg = <0xe1810000 0x100>; 569 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 571 clock-names = "aes_clk"; 572 dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, 573 <&dma0 AT91_XDMAC_DT_PERID(2)>; 574 dma-names = "tx", "rx"; 575 }; 576 577 sha: crypto@e1814000 { 578 compatible = "atmel,at91sam9g46-sha"; 579 reg = <0xe1814000 0x100>; 580 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&pmc PMC_TYPE_PERIPHERAL 83>; 582 clock-names = "sha_clk"; 583 dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; 584 dma-names = "tx"; 585 }; 586 587 flx0: flexcom@e1818000 { 588 compatible = "atmel,sama5d2-flexcom"; 589 reg = <0xe1818000 0x200>; 590 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 591 #address-cells = <1>; 592 #size-cells = <1>; 593 ranges = <0x0 0xe1818000 0x800>; 594 status = "disabled"; 595 596 uart0: serial@200 { 597 compatible = "atmel,at91sam9260-usart"; 598 reg = <0x200 0x200>; 599 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 601 clock-names = "usart"; 602 dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, 603 <&dma1 AT91_XDMAC_DT_PERID(5)>; 604 dma-names = "tx", "rx"; 605 atmel,use-dma-rx; 606 atmel,use-dma-tx; 607 status = "disabled"; 608 }; 609 }; 610 611 flx1: flexcom@e181c000 { 612 compatible = "atmel,sama5d2-flexcom"; 613 reg = <0xe181c000 0x200>; 614 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 615 #address-cells = <1>; 616 #size-cells = <1>; 617 ranges = <0x0 0xe181c000 0x800>; 618 status = "disabled"; 619 620 i2c1: i2c@600 { 621 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 622 reg = <0x600 0x200>; 623 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 624 #address-cells = <1>; 625 #size-cells = <0>; 626 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 627 atmel,fifo-size = <32>; 628 dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, 629 <&dma0 AT91_XDMAC_DT_PERID(7)>; 630 dma-names = "tx", "rx"; 631 status = "disabled"; 632 }; 633 }; 634 635 flx3: flexcom@e1824000 { 636 compatible = "atmel,sama5d2-flexcom"; 637 reg = <0xe1824000 0x200>; 638 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 639 #address-cells = <1>; 640 #size-cells = <1>; 641 ranges = <0x0 0xe1824000 0x800>; 642 status = "disabled"; 643 644 uart3: serial@200 { 645 compatible = "atmel,at91sam9260-usart"; 646 reg = <0x200 0x200>; 647 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 649 clock-names = "usart"; 650 dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>, 651 <&dma1 AT91_XDMAC_DT_PERID(11)>; 652 dma-names = "tx", "rx"; 653 atmel,use-dma-rx; 654 atmel,use-dma-tx; 655 status = "disabled"; 656 }; 657 }; 658 659 trng: rng@e2010000 { 660 compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng"; 661 reg = <0xe2010000 0x100>; 662 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&pmc PMC_TYPE_PERIPHERAL 97>; 664 status = "disabled"; 665 }; 666 667 tdes: crypto@e2014000 { 668 compatible = "atmel,at91sam9g46-tdes"; 669 reg = <0xe2014000 0x100>; 670 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&pmc PMC_TYPE_PERIPHERAL 96>; 672 clock-names = "tdes_clk"; 673 dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, 674 <&dma0 AT91_XDMAC_DT_PERID(53)>; 675 dma-names = "tx", "rx"; 676 }; 677 678 flx4: flexcom@e2018000 { 679 compatible = "atmel,sama5d2-flexcom"; 680 reg = <0xe2018000 0x200>; 681 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 682 #address-cells = <1>; 683 #size-cells = <1>; 684 ranges = <0x0 0xe2018000 0x800>; 685 status = "disabled"; 686 687 uart4: serial@200 { 688 compatible = "atmel,at91sam9260-usart"; 689 reg = <0x200 0x200>; 690 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 692 clock-names = "usart"; 693 dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, 694 <&dma1 AT91_XDMAC_DT_PERID(13)>; 695 dma-names = "tx", "rx"; 696 atmel,use-dma-rx; 697 atmel,use-dma-tx; 698 atmel,fifo-size = <16>; 699 status = "disabled"; 700 }; 701 }; 702 703 flx7: flexcom@e2024000 { 704 compatible = "atmel,sama5d2-flexcom"; 705 reg = <0xe2024000 0x200>; 706 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; 707 #address-cells = <1>; 708 #size-cells = <1>; 709 ranges = <0x0 0xe2024000 0x800>; 710 status = "disabled"; 711 712 uart7: serial@200 { 713 compatible = "atmel,at91sam9260-usart"; 714 reg = <0x200 0x200>; 715 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; 717 clock-names = "usart"; 718 dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, 719 <&dma1 AT91_XDMAC_DT_PERID(19)>; 720 dma-names = "tx", "rx"; 721 atmel,use-dma-rx; 722 atmel,use-dma-tx; 723 atmel,fifo-size = <16>; 724 status = "disabled"; 725 }; 726 }; 727 728 gmac0: ethernet@e2800000 { 729 compatible = "microchip,sama7g5-gem"; 730 reg = <0xe2800000 0x1000>; 731 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 732 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 733 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 734 GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 735 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 736 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>; 738 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; 739 assigned-clocks = <&pmc PMC_TYPE_GCK 51>; 740 assigned-clock-rates = <125000000>; 741 status = "disabled"; 742 }; 743 744 gmac1: ethernet@e2804000 { 745 compatible = "microchip,sama7g5-emac"; 746 reg = <0xe2804000 0x1000>; 747 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 748 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>; 750 clock-names = "pclk", "hclk"; 751 status = "disabled"; 752 }; 753 754 dma0: dma-controller@e2808000 { 755 compatible = "microchip,sama7g5-dma"; 756 reg = <0xe2808000 0x1000>; 757 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 758 #dma-cells = <1>; 759 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 760 clock-names = "dma_clk"; 761 status = "disabled"; 762 }; 763 764 dma1: dma-controller@e280c000 { 765 compatible = "microchip,sama7g5-dma"; 766 reg = <0xe280c000 0x1000>; 767 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 768 #dma-cells = <1>; 769 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 770 clock-names = "dma_clk"; 771 status = "disabled"; 772 }; 773 774 /* Place dma2 here despite it's address */ 775 dma2: dma-controller@e1200000 { 776 compatible = "microchip,sama7g5-dma"; 777 reg = <0xe1200000 0x1000>; 778 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 779 #dma-cells = <1>; 780 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 781 clock-names = "dma_clk"; 782 dma-requests = <0>; 783 status = "disabled"; 784 }; 785 786 tcb0: timer@e2814000 { 787 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 reg = <0xe2814000 0x100>; 791 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>; 793 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 794 }; 795 796 flx8: flexcom@e2818000 { 797 compatible = "atmel,sama5d2-flexcom"; 798 reg = <0xe2818000 0x200>; 799 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; 800 #address-cells = <1>; 801 #size-cells = <1>; 802 ranges = <0x0 0xe2818000 0x800>; 803 status = "disabled"; 804 805 i2c8: i2c@600 { 806 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 807 reg = <0x600 0x200>; 808 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 809 #address-cells = <1>; 810 #size-cells = <0>; 811 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; 812 atmel,fifo-size = <32>; 813 dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, 814 <&dma0 AT91_XDMAC_DT_PERID(21)>; 815 dma-names = "tx", "rx"; 816 status = "disabled"; 817 }; 818 }; 819 820 flx9: flexcom@e281c000 { 821 compatible = "atmel,sama5d2-flexcom"; 822 reg = <0xe281c000 0x200>; 823 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 824 #address-cells = <1>; 825 #size-cells = <1>; 826 ranges = <0x0 0xe281c000 0x800>; 827 status = "disabled"; 828 829 i2c9: i2c@600 { 830 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 831 reg = <0x600 0x200>; 832 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 836 atmel,fifo-size = <32>; 837 dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, 838 <&dma0 AT91_XDMAC_DT_PERID(23)>; 839 dma-names = "tx", "rx"; 840 status = "disabled"; 841 }; 842 }; 843 844 flx11: flexcom@e2824000 { 845 compatible = "atmel,sama5d2-flexcom"; 846 reg = <0xe2824000 0x200>; 847 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; 848 #address-cells = <1>; 849 #size-cells = <1>; 850 ranges = <0x0 0xe2824000 0x800>; 851 status = "disabled"; 852 853 spi11: spi@400 { 854 compatible = "atmel,at91rm9200-spi"; 855 reg = <0x400 0x200>; 856 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; 858 clock-names = "spi_clk"; 859 #address-cells = <1>; 860 #size-cells = <0>; 861 atmel,fifo-size = <32>; 862 dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>, 863 <&dma0 AT91_XDMAC_DT_PERID(28)>; 864 dma-names = "rx", "tx"; 865 status = "disabled"; 866 }; 867 }; 868 869 uddrc: uddrc@e3800000 { 870 compatible = "microchip,sama7g5-uddrc"; 871 reg = <0xe3800000 0x4000>; 872 }; 873 874 ddr3phy: ddr3phy@e3804000 { 875 compatible = "microchip,sama7g5-ddr3phy"; 876 reg = <0xe3804000 0x1000>; 877 }; 878 879 gic: interrupt-controller@e8c11000 { 880 compatible = "arm,cortex-a7-gic"; 881 #interrupt-cells = <3>; 882 #address-cells = <0>; 883 interrupt-controller; 884 reg = <0xe8c11000 0x1000>, 885 <0xe8c12000 0x2000>; 886 }; 887 }; 888};