cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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spear310.dtsi (2738B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * DTS file for SPEAr310 SoC
      4 *
      5 * Copyright 2012 Viresh Kumar <vireshk@kernel.org>
      6 */
      7
      8/include/ "spear3xx.dtsi"
      9
     10/ {
     11	ahb {
     12		#address-cells = <1>;
     13		#size-cells = <1>;
     14		compatible = "simple-bus";
     15		ranges = <0x40000000 0x40000000 0x10000000
     16			  0xb0000000 0xb0000000 0x10000000
     17			  0xd0000000 0xd0000000 0x30000000>;
     18
     19		pinmux: pinmux@b4000000 {
     20			compatible = "st,spear310-pinmux";
     21			reg = <0xb4000000 0x1000>;
     22			#gpio-range-cells = <3>;
     23		};
     24
     25		fsmc: flash@44000000 {
     26			compatible = "st,spear600-fsmc-nand";
     27			#address-cells = <1>;
     28			#size-cells = <1>;
     29			reg = <0x44000000 0x1000	/* FSMC Register */
     30			       0x40000000 0x0010	/* NAND Base DATA */
     31			       0x40020000 0x0010	/* NAND Base ADDR */
     32			       0x40010000 0x0010>;	/* NAND Base CMD */
     33			reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
     34			status = "disabled";
     35		};
     36
     37		shirq: interrupt-controller@0xb4000000 {
     38			compatible = "st,spear310-shirq";
     39			reg = <0xb4000000 0x1000>;
     40			interrupts = <28 29 30 1>;
     41			#interrupt-cells = <1>;
     42			interrupt-controller;
     43		};
     44
     45		apb {
     46			#address-cells = <1>;
     47			#size-cells = <1>;
     48			compatible = "simple-bus";
     49			ranges = <0xb0000000 0xb0000000 0x10000000
     50				  0xd0000000 0xd0000000 0x30000000>;
     51
     52			serial@b2000000 {
     53				compatible = "arm,pl011", "arm,primecell";
     54				reg = <0xb2000000 0x1000>;
     55				interrupts = <8>;
     56				interrupt-parent = <&shirq>;
     57				status = "disabled";
     58			};
     59
     60			serial@b2080000 {
     61				compatible = "arm,pl011", "arm,primecell";
     62				reg = <0xb2080000 0x1000>;
     63				interrupts = <9>;
     64				interrupt-parent = <&shirq>;
     65				status = "disabled";
     66			};
     67
     68			serial@b2100000 {
     69				compatible = "arm,pl011", "arm,primecell";
     70				reg = <0xb2100000 0x1000>;
     71				interrupts = <10>;
     72				interrupt-parent = <&shirq>;
     73				status = "disabled";
     74			};
     75
     76			serial@b2180000 {
     77				compatible = "arm,pl011", "arm,primecell";
     78				reg = <0xb2180000 0x1000>;
     79				interrupts = <11>;
     80				interrupt-parent = <&shirq>;
     81				status = "disabled";
     82			};
     83
     84			serial@b2200000 {
     85				compatible = "arm,pl011", "arm,primecell";
     86				reg = <0xb2200000 0x1000>;
     87				interrupts = <12>;
     88				interrupt-parent = <&shirq>;
     89				status = "disabled";
     90			};
     91
     92			gpiopinctrl: gpio@b4000000 {
     93				compatible = "st,spear-plgpio";
     94				reg = <0xb4000000 0x1000>;
     95				regmap = <&pinmux>;
     96				#interrupt-cells = <1>;
     97				interrupt-controller;
     98				gpio-controller;
     99				#gpio-cells = <2>;
    100				gpio-ranges = <&pinmux 0 0 102>;
    101				status = "disabled";
    102
    103				st-plgpio,ngpio = <102>;
    104				st-plgpio,enb-reg = <0x10>;
    105				st-plgpio,wdata-reg = <0x20>;
    106				st-plgpio,dir-reg = <0x30>;
    107				st-plgpio,ie-reg = <0x50>;
    108				st-plgpio,rdata-reg = <0x40>;
    109				st-plgpio,mis-reg = <0x60>;
    110			};
    111		};
    112	};
    113};