cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

ste-hrefprev60.dtsi (2437B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Copyright 2012 ST-Ericsson AB
      4 *
      5 * Device Tree for the HREF+ prior to the v60 variant.
      6 */
      7
      8#include "ste-href-ab8500.dtsi"
      9#include "ste-href.dtsi"
     10
     11/ {
     12	gpio_keys {
     13		button@1 {
     14			gpios = <&tc3589x_gpio 7 GPIO_ACTIVE_HIGH>;
     15		};
     16	};
     17
     18	soc {
     19		/* Enable UART1 on this board */
     20		uart@80121000 {
     21			status = "okay";
     22		};
     23
     24		i2c@80004000 {
     25			tps61052@33 {
     26				compatible = "ti,tps61052";
     27				reg = <0x33>;
     28			};
     29
     30			tc35892@42 {
     31				compatible = "toshiba,tc35892";
     32				reg = <0x42>;
     33				interrupt-parent = <&gpio6>;
     34				interrupts = <25 IRQ_TYPE_EDGE_RISING>;
     35				pinctrl-names = "default";
     36				pinctrl-0 = <&tc35892_hrefprev60_mode>;
     37
     38				interrupt-controller;
     39				#interrupt-cells = <1>;
     40
     41				tc3589x_gpio: tc3589x_gpio {
     42					compatible = "tc3589x-gpio";
     43					interrupts = <0>;
     44
     45					interrupt-controller;
     46					#interrupt-cells = <2>;
     47					gpio-controller;
     48					#gpio-cells = <2>;
     49				};
     50			};
     51		};
     52
     53		spi@80002000 {
     54			/*
     55			 * On the first generation boards, this SSP/SPI port was connected
     56			 * to the AB8500.
     57			 */
     58			pinctrl-names = "default";
     59			pinctrl-0 = <&ssp0_hrefprev60_mode>;
     60			status = "okay";
     61		};
     62
     63		// External Micro SD slot
     64		mmc@80126000 {
     65			cd-gpios  = <&tc3589x_gpio 3 GPIO_ACTIVE_HIGH>;
     66		};
     67
     68		pinctrl {
     69			/* Set this up using hogs */
     70			pinctrl-names = "default";
     71			pinctrl-0 = <&ipgpio_hrefprev60_mode>;
     72
     73			ssp0 {
     74				ssp0_hrefprev60_mode: ssp0_hrefprev60_default {
     75					hrefprev60_mux {
     76						function = "ssp0";
     77						groups = "ssp0_a_1";
     78					};
     79					hrefprev60_cfg1 {
     80						pins = "GPIO145_C13"; /* RXD */
     81						ste,config = <&in_pd>;
     82					};
     83
     84				};
     85			};
     86			sdi0 {
     87				/* This additional pin needed on early MOP500 and HREFs previous to v60 */
     88				sdi0_default_mode: sdi0_default {
     89					hrefprev60_mux {
     90						function = "mc0";
     91						groups = "mc0dat31dir_a_1";
     92					};
     93					hrefprev60_cfg1 {
     94						pins = "GPIO21_AB3"; /* DAT31DIR */
     95						ste,config = <&out_hi>;
     96					};
     97
     98				};
     99			};
    100			tc35892 {
    101				tc35892_hrefprev60_mode: tc35892_hrefprev60 {
    102					hrefprev60_cfg {
    103						pins = "GPIO217_AH12";
    104						ste,config = <&gpio_in_pu>;
    105					};
    106				};
    107			};
    108			ipgpio {
    109				 ipgpio_hrefprev60_mode: ipgpio_hrefprev60 {
    110					hrefprev60_mux {
    111						function = "ipgpio";
    112						groups = "ipgpio0_c_1", "ipgpio1_c_1";
    113					};
    114					hrefprev60_cfg1 {
    115						pins = "GPIO6_AF6", "GPIO7_AG5";
    116						ste,config = <&in_pu>;
    117					};
    118				 };
    119			};
    120		};
    121	};
    122};