ste-nomadik-stn8815.dtsi (20569B)
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7 8/ { 9 #address-cells = <1>; 10 #size-cells = <1>; 11 12 memory { 13 device_type = "memory"; 14 reg = <0x00000000 0x04000000>, 15 <0x08000000 0x04000000>; 16 }; 17 18 L2: cache-controller { 19 compatible = "arm,l210-cache"; 20 reg = <0x10210000 0x1000>; 21 interrupt-parent = <&vica>; 22 interrupts = <30>; 23 cache-unified; 24 cache-level = <2>; 25 cache-size = <131072>; 26 cache-sets = <512>; 27 cache-line-size = <32>; 28 /* At full speed latency must be >=2 */ 29 arm,tag-latency = <8>; 30 arm,data-latency = <8 8>; 31 arm,dirty-latency = <8>; 32 }; 33 34 mtu0: mtu@101e2000 { 35 /* Nomadik system timer */ 36 compatible = "st,nomadik-mtu"; 37 reg = <0x101e2000 0x1000>; 38 interrupt-parent = <&vica>; 39 interrupts = <4>; 40 clocks = <&timclk>, <&pclk>; 41 clock-names = "timclk", "apb_pclk"; 42 }; 43 44 mtu1: mtu@101e3000 { 45 /* Secondary timer */ 46 reg = <0x101e3000 0x1000>; 47 interrupt-parent = <&vica>; 48 interrupts = <5>; 49 clocks = <&timclk>, <&pclk>; 50 clock-names = "timclk", "apb_pclk"; 51 }; 52 53 gpio0: gpio@101e4000 { 54 compatible = "st,nomadik-gpio"; 55 reg = <0x101e4000 0x80>; 56 interrupt-parent = <&vica>; 57 interrupts = <6>; 58 interrupt-controller; 59 #interrupt-cells = <2>; 60 gpio-controller; 61 #gpio-cells = <2>; 62 gpio-bank = <0>; 63 gpio-ranges = <&pinctrl 0 0 32>; 64 clocks = <&pclk>; 65 }; 66 67 gpio1: gpio@101e5000 { 68 compatible = "st,nomadik-gpio"; 69 reg = <0x101e5000 0x80>; 70 interrupt-parent = <&vica>; 71 interrupts = <7>; 72 interrupt-controller; 73 #interrupt-cells = <2>; 74 gpio-controller; 75 #gpio-cells = <2>; 76 gpio-bank = <1>; 77 gpio-ranges = <&pinctrl 0 32 32>; 78 clocks = <&pclk>; 79 }; 80 81 gpio2: gpio@101e6000 { 82 compatible = "st,nomadik-gpio"; 83 reg = <0x101e6000 0x80>; 84 interrupt-parent = <&vica>; 85 interrupts = <8>; 86 interrupt-controller; 87 #interrupt-cells = <2>; 88 gpio-controller; 89 #gpio-cells = <2>; 90 gpio-bank = <2>; 91 gpio-ranges = <&pinctrl 0 64 32>; 92 clocks = <&pclk>; 93 }; 94 95 gpio3: gpio@101e7000 { 96 compatible = "st,nomadik-gpio"; 97 reg = <0x101e7000 0x80>; 98 ngpio = <28>; 99 interrupt-parent = <&vica>; 100 interrupts = <9>; 101 interrupt-controller; 102 #interrupt-cells = <2>; 103 gpio-controller; 104 #gpio-cells = <2>; 105 gpio-bank = <3>; 106 gpio-ranges = <&pinctrl 0 96 28>; 107 clocks = <&pclk>; 108 }; 109 110 pinctrl: pinctrl { 111 compatible = "stericsson,stn8815-pinctrl"; 112 nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>; 113 /* Pin configurations */ 114 uart1 { 115 uart1_default_mux: uart1_mux { 116 u1_default_mux { 117 function = "u1"; 118 groups = "u1_a_1"; 119 }; 120 }; 121 }; 122 mmcsd { 123 mmcsd_default_mux: mmcsd_mux { 124 mmcsd_default_mux { 125 function = "mmcsd"; 126 groups = "mmcsd_a_1", "mmcsd_b_1"; 127 }; 128 }; 129 mmcsd_default_mode: mmcsd_default { 130 mmcsd_default_cfg1 { 131 /* 132 * MCCLK, MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 133 * MCCMD, MCDAT3-0, MCMSFBCLK 134 */ 135 pins = "GPIO8_B10", "GPIO9_A10", "GPIO10_C11", "GPIO11_B11", 136 "GPIO12_A11", "GPIO13_C12", "GPIO14_B12", "GPIO15_A12", 137 "GPIO16_C13", "GPIO23_D15", "GPIO24_C15"; 138 ste,output = <2>; 139 }; 140 }; 141 }; 142 i2c0 { 143 i2c0_default_mux: i2c0_mux { 144 i2c0_default_mux { 145 function = "i2c0"; 146 groups = "i2c0_a_1"; 147 }; 148 }; 149 i2c0_default_mode: i2c0_default { 150 i2c0_default_cfg { 151 pins = "GPIO62_D3", "GPIO63_D2"; 152 ste,input = <0>; 153 }; 154 }; 155 }; 156 i2c1 { 157 i2c1_default_mux: i2c1_mux { 158 i2c1_default_mux { 159 function = "i2c1"; 160 groups = "i2c1_a_1"; 161 }; 162 }; 163 i2c1_default_mode: i2c1_default { 164 i2c1_default_cfg { 165 pins = "GPIO53_L4", "GPIO54_L3"; 166 ste,input = <0>; 167 }; 168 }; 169 }; 170 clcd { 171 /* 172 * This should be activated to use the additional 173 * 8 lines for bits 16 thru 23 from the CLCD block. 174 */ 175 clcd_24bit_mux: clcd_mux { 176 clcd_24bit_mux { 177 function = "clcd"; 178 groups = "clcd_16_23_b_1"; 179 }; 180 }; 181 }; 182 }; 183 184 /* Power Management Unit */ 185 pmu: pmu@101e9000 { 186 compatible = "stericsson,nomadik-pmu", "syscon"; 187 reg = <0x101e0000 0x1000>; 188 }; 189 190 src: src@101e0000 { 191 compatible = "stericsson,nomadik-src"; 192 reg = <0x101e0000 0x1000>; 193 194 /* 195 * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz 196 * that is parent of TIMCLK, PLL1 and PLL2 197 */ 198 mxtal: mxtal@19.2M { 199 #clock-cells = <0>; 200 compatible = "fixed-clock"; 201 clock-frequency = <19200000>; 202 }; 203 204 /* 205 * The 2.4 MHz TIMCLK reference clock is active at 206 * boot time, this is actually the MXTALCLK @19.2 MHz 207 * divided by 8. This clock is used by the timers and 208 * watchdog. See page 105 ff. 209 */ 210 timclk: timclk@2.4M { 211 #clock-cells = <0>; 212 compatible = "fixed-factor-clock"; 213 clock-div = <8>; 214 clock-mult = <1>; 215 clocks = <&mxtal>; 216 }; 217 218 /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */ 219 pll1: pll1@0 { 220 #clock-cells = <0>; 221 compatible = "st,nomadik-pll-clock"; 222 pll-id = <1>; 223 clocks = <&mxtal>; 224 }; 225 226 /* HCLK divides the PLL1 with 1,2,3 or 4 */ 227 hclk: hclk@0 { 228 #clock-cells = <0>; 229 compatible = "st,nomadik-hclk-clock"; 230 clocks = <&pll1>; 231 }; 232 /* The PCLK domain uses HCLK right off */ 233 pclk: pclk@0 { 234 #clock-cells = <0>; 235 compatible = "fixed-factor-clock"; 236 clock-div = <1>; 237 clock-mult = <1>; 238 clocks = <&hclk>; 239 }; 240 241 /* PLL2 is usually 864 MHz and divided into a few fixed rates */ 242 pll2: pll2@0 { 243 #clock-cells = <0>; 244 compatible = "st,nomadik-pll-clock"; 245 pll-id = <2>; 246 clocks = <&mxtal>; 247 }; 248 clk216: clk216@216M { 249 #clock-cells = <0>; 250 compatible = "fixed-factor-clock"; 251 clock-div = <4>; 252 clock-mult = <1>; 253 clocks = <&pll2>; 254 }; 255 clk108: clk108@108M { 256 #clock-cells = <0>; 257 compatible = "fixed-factor-clock"; 258 clock-div = <2>; 259 clock-mult = <1>; 260 clocks = <&clk216>; 261 }; 262 clk72: clk72@72M { 263 #clock-cells = <0>; 264 compatible = "fixed-factor-clock"; 265 /* The data sheet does not say how this is derived */ 266 clock-div = <12>; 267 clock-mult = <1>; 268 clocks = <&pll2>; 269 }; 270 clk48: clk48@48M { 271 #clock-cells = <0>; 272 compatible = "fixed-factor-clock"; 273 /* The data sheet does not say how this is derived */ 274 clock-div = <18>; 275 clock-mult = <1>; 276 clocks = <&pll2>; 277 }; 278 clk27: clk27@27M { 279 #clock-cells = <0>; 280 compatible = "fixed-factor-clock"; 281 clock-div = <4>; 282 clock-mult = <1>; 283 clocks = <&clk108>; 284 }; 285 286 /* This apparently exists as well */ 287 ulpiclk: ulpiclk@60M { 288 #clock-cells = <0>; 289 compatible = "fixed-clock"; 290 clock-frequency = <60000000>; 291 }; 292 293 /* 294 * IP AMBA bus clocks, driving the bus side of the 295 * peripheral clocking, clock gates. 296 */ 297 298 hclkdma0: hclkdma0@48M { 299 #clock-cells = <0>; 300 compatible = "st,nomadik-src-clock"; 301 clock-id = <0>; 302 clocks = <&hclk>; 303 }; 304 hclksmc: hclksmc@48M { 305 #clock-cells = <0>; 306 compatible = "st,nomadik-src-clock"; 307 clock-id = <1>; 308 clocks = <&hclk>; 309 }; 310 hclksdram: hclksdram@48M { 311 #clock-cells = <0>; 312 compatible = "st,nomadik-src-clock"; 313 clock-id = <2>; 314 clocks = <&hclk>; 315 }; 316 hclkdma1: hclkdma1@48M { 317 #clock-cells = <0>; 318 compatible = "st,nomadik-src-clock"; 319 clock-id = <3>; 320 clocks = <&hclk>; 321 }; 322 hclkclcd: hclkclcd@48M { 323 #clock-cells = <0>; 324 compatible = "st,nomadik-src-clock"; 325 clock-id = <4>; 326 clocks = <&hclk>; 327 }; 328 pclkirda: pclkirda@48M { 329 #clock-cells = <0>; 330 compatible = "st,nomadik-src-clock"; 331 clock-id = <5>; 332 clocks = <&pclk>; 333 }; 334 pclkssp: pclkssp@48M { 335 #clock-cells = <0>; 336 compatible = "st,nomadik-src-clock"; 337 clock-id = <6>; 338 clocks = <&pclk>; 339 }; 340 pclkuart0: pclkuart0@48M { 341 #clock-cells = <0>; 342 compatible = "st,nomadik-src-clock"; 343 clock-id = <7>; 344 clocks = <&pclk>; 345 }; 346 pclksdi: pclksdi@48M { 347 #clock-cells = <0>; 348 compatible = "st,nomadik-src-clock"; 349 clock-id = <8>; 350 clocks = <&pclk>; 351 }; 352 pclki2c0: pclki2c0@48M { 353 #clock-cells = <0>; 354 compatible = "st,nomadik-src-clock"; 355 clock-id = <9>; 356 clocks = <&pclk>; 357 }; 358 pclki2c1: pclki2c1@48M { 359 #clock-cells = <0>; 360 compatible = "st,nomadik-src-clock"; 361 clock-id = <10>; 362 clocks = <&pclk>; 363 }; 364 pclkuart1: pclkuart1@48M { 365 #clock-cells = <0>; 366 compatible = "st,nomadik-src-clock"; 367 clock-id = <11>; 368 clocks = <&pclk>; 369 }; 370 pclkmsp0: pclkmsp0@48M { 371 #clock-cells = <0>; 372 compatible = "st,nomadik-src-clock"; 373 clock-id = <12>; 374 clocks = <&pclk>; 375 }; 376 hclkusb: hclkusb@48M { 377 #clock-cells = <0>; 378 compatible = "st,nomadik-src-clock"; 379 clock-id = <13>; 380 clocks = <&hclk>; 381 }; 382 hclkdif: hclkdif@48M { 383 #clock-cells = <0>; 384 compatible = "st,nomadik-src-clock"; 385 clock-id = <14>; 386 clocks = <&hclk>; 387 }; 388 hclksaa: hclksaa@48M { 389 #clock-cells = <0>; 390 compatible = "st,nomadik-src-clock"; 391 clock-id = <15>; 392 clocks = <&hclk>; 393 }; 394 hclksva: hclksva@48M { 395 #clock-cells = <0>; 396 compatible = "st,nomadik-src-clock"; 397 clock-id = <16>; 398 clocks = <&hclk>; 399 }; 400 pclkhsi: pclkhsi@48M { 401 #clock-cells = <0>; 402 compatible = "st,nomadik-src-clock"; 403 clock-id = <17>; 404 clocks = <&pclk>; 405 }; 406 pclkxti: pclkxti@48M { 407 #clock-cells = <0>; 408 compatible = "st,nomadik-src-clock"; 409 clock-id = <18>; 410 clocks = <&pclk>; 411 }; 412 pclkuart2: pclkuart2@48M { 413 #clock-cells = <0>; 414 compatible = "st,nomadik-src-clock"; 415 clock-id = <19>; 416 clocks = <&pclk>; 417 }; 418 pclkmsp1: pclkmsp1@48M { 419 #clock-cells = <0>; 420 compatible = "st,nomadik-src-clock"; 421 clock-id = <20>; 422 clocks = <&pclk>; 423 }; 424 pclkmsp2: pclkmsp2@48M { 425 #clock-cells = <0>; 426 compatible = "st,nomadik-src-clock"; 427 clock-id = <21>; 428 clocks = <&pclk>; 429 }; 430 pclkowm: pclkowm@48M { 431 #clock-cells = <0>; 432 compatible = "st,nomadik-src-clock"; 433 clock-id = <22>; 434 clocks = <&pclk>; 435 }; 436 hclkhpi: hclkhpi@48M { 437 #clock-cells = <0>; 438 compatible = "st,nomadik-src-clock"; 439 clock-id = <23>; 440 clocks = <&hclk>; 441 }; 442 pclkske: pclkske@48M { 443 #clock-cells = <0>; 444 compatible = "st,nomadik-src-clock"; 445 clock-id = <24>; 446 clocks = <&pclk>; 447 }; 448 pclkhsem: pclkhsem@48M { 449 #clock-cells = <0>; 450 compatible = "st,nomadik-src-clock"; 451 clock-id = <25>; 452 clocks = <&pclk>; 453 }; 454 hclk3d: hclk3d@48M { 455 #clock-cells = <0>; 456 compatible = "st,nomadik-src-clock"; 457 clock-id = <26>; 458 clocks = <&hclk>; 459 }; 460 hclkhash: hclkhash@48M { 461 #clock-cells = <0>; 462 compatible = "st,nomadik-src-clock"; 463 clock-id = <27>; 464 clocks = <&hclk>; 465 }; 466 hclkcryp: hclkcryp@48M { 467 #clock-cells = <0>; 468 compatible = "st,nomadik-src-clock"; 469 clock-id = <28>; 470 clocks = <&hclk>; 471 }; 472 pclkmshc: pclkmshc@48M { 473 #clock-cells = <0>; 474 compatible = "st,nomadik-src-clock"; 475 clock-id = <29>; 476 clocks = <&pclk>; 477 }; 478 hclkusbm: hclkusbm@48M { 479 #clock-cells = <0>; 480 compatible = "st,nomadik-src-clock"; 481 clock-id = <30>; 482 clocks = <&hclk>; 483 }; 484 hclkrng: hclkrng@48M { 485 #clock-cells = <0>; 486 compatible = "st,nomadik-src-clock"; 487 clock-id = <31>; 488 clocks = <&hclk>; 489 }; 490 491 /* IP kernel clocks */ 492 clcdclk: clcdclk@0 { 493 #clock-cells = <0>; 494 compatible = "st,nomadik-src-clock"; 495 clock-id = <36>; 496 clocks = <&clk72 &clk48>; 497 }; 498 irdaclk: irdaclk@48M { 499 #clock-cells = <0>; 500 compatible = "st,nomadik-src-clock"; 501 clock-id = <37>; 502 clocks = <&clk48>; 503 }; 504 sspiclk: sspiclk@48M { 505 #clock-cells = <0>; 506 compatible = "st,nomadik-src-clock"; 507 clock-id = <38>; 508 clocks = <&clk48>; 509 }; 510 uart0clk: uart0clk@48M { 511 #clock-cells = <0>; 512 compatible = "st,nomadik-src-clock"; 513 clock-id = <39>; 514 clocks = <&clk48>; 515 }; 516 sdiclk: sdiclk@48M { 517 /* Also called MCCLK in some documents */ 518 #clock-cells = <0>; 519 compatible = "st,nomadik-src-clock"; 520 clock-id = <40>; 521 clocks = <&clk48>; 522 }; 523 i2c0clk: i2c0clk@48M { 524 #clock-cells = <0>; 525 compatible = "st,nomadik-src-clock"; 526 clock-id = <41>; 527 clocks = <&clk48>; 528 }; 529 i2c1clk: i2c1clk@48M { 530 #clock-cells = <0>; 531 compatible = "st,nomadik-src-clock"; 532 clock-id = <42>; 533 clocks = <&clk48>; 534 }; 535 uart1clk: uart1clk@48M { 536 #clock-cells = <0>; 537 compatible = "st,nomadik-src-clock"; 538 clock-id = <43>; 539 clocks = <&clk48>; 540 }; 541 mspclk0: mspclk0@48M { 542 #clock-cells = <0>; 543 compatible = "st,nomadik-src-clock"; 544 clock-id = <44>; 545 clocks = <&clk48>; 546 }; 547 usbclk: usbclk@48M { 548 #clock-cells = <0>; 549 compatible = "st,nomadik-src-clock"; 550 clock-id = <45>; 551 clocks = <&clk48>; /* 48 MHz not ULPI */ 552 }; 553 difclk: difclk@72M { 554 #clock-cells = <0>; 555 compatible = "st,nomadik-src-clock"; 556 clock-id = <46>; 557 clocks = <&clk72>; 558 }; 559 ipi2cclk: ipi2cclk@48M { 560 #clock-cells = <0>; 561 compatible = "st,nomadik-src-clock"; 562 clock-id = <47>; 563 clocks = <&clk48>; /* Guess */ 564 }; 565 ipbmcclk: ipbmcclk@48M { 566 #clock-cells = <0>; 567 compatible = "st,nomadik-src-clock"; 568 clock-id = <48>; 569 clocks = <&clk48>; /* Guess */ 570 }; 571 hsiclkrx: hsiclkrx@216M { 572 #clock-cells = <0>; 573 compatible = "st,nomadik-src-clock"; 574 clock-id = <49>; 575 clocks = <&clk216>; 576 }; 577 hsiclktx: hsiclktx@108M { 578 #clock-cells = <0>; 579 compatible = "st,nomadik-src-clock"; 580 clock-id = <50>; 581 clocks = <&clk108>; 582 }; 583 uart2clk: uart2clk@48M { 584 #clock-cells = <0>; 585 compatible = "st,nomadik-src-clock"; 586 clock-id = <51>; 587 clocks = <&clk48>; 588 }; 589 mspclk1: mspclk1@48M { 590 #clock-cells = <0>; 591 compatible = "st,nomadik-src-clock"; 592 clock-id = <52>; 593 clocks = <&clk48>; 594 }; 595 mspclk2: mspclk2@48M { 596 #clock-cells = <0>; 597 compatible = "st,nomadik-src-clock"; 598 clock-id = <53>; 599 clocks = <&clk48>; 600 }; 601 owmclk: owmclk@48M { 602 #clock-cells = <0>; 603 compatible = "st,nomadik-src-clock"; 604 clock-id = <54>; 605 clocks = <&clk48>; /* Guess */ 606 }; 607 skeclk: skeclk@48M { 608 #clock-cells = <0>; 609 compatible = "st,nomadik-src-clock"; 610 clock-id = <56>; 611 clocks = <&clk48>; /* Guess */ 612 }; 613 x3dclk: x3dclk@48M { 614 #clock-cells = <0>; 615 compatible = "st,nomadik-src-clock"; 616 clock-id = <58>; 617 clocks = <&clk48>; /* Guess */ 618 }; 619 pclkmsp3: pclkmsp3@48M { 620 #clock-cells = <0>; 621 compatible = "st,nomadik-src-clock"; 622 clock-id = <59>; 623 clocks = <&pclk>; 624 }; 625 mspclk3: mspclk3@48M { 626 #clock-cells = <0>; 627 compatible = "st,nomadik-src-clock"; 628 clock-id = <60>; 629 clocks = <&clk48>; 630 }; 631 mshcclk: mshcclk@48M { 632 #clock-cells = <0>; 633 compatible = "st,nomadik-src-clock"; 634 clock-id = <61>; 635 clocks = <&clk48>; /* Guess */ 636 }; 637 usbmclk: usbmclk@48M { 638 #clock-cells = <0>; 639 compatible = "st,nomadik-src-clock"; 640 clock-id = <62>; 641 /* Stated as "48 MHz not ULPI clock" */ 642 clocks = <&clk48>; 643 }; 644 rngcclk: rngcclk@48M { 645 #clock-cells = <0>; 646 compatible = "st,nomadik-src-clock"; 647 clock-id = <63>; 648 clocks = <&clk48>; /* Guess */ 649 }; 650 }; 651 652 /* A NAND flash of 128 MiB */ 653 fsmc: flash@40000000 { 654 compatible = "stericsson,fsmc-nand"; 655 #address-cells = <1>; 656 #size-cells = <1>; 657 reg = <0x10100000 0x1000>, /* FSMC Register*/ 658 <0x40000000 0x2000>, /* NAND Base DATA */ 659 <0x41000000 0x2000>, /* NAND Base ADDR */ 660 <0x40800000 0x2000>; /* NAND Base CMD */ 661 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; 662 clocks = <&hclksmc>; 663 status = "okay"; 664 665 partition@0 { 666 label = "X-Loader(NAND)"; 667 reg = <0x0 0x40000>; 668 }; 669 partition@40000 { 670 label = "MemInit(NAND)"; 671 reg = <0x40000 0x40000>; 672 }; 673 partition@80000 { 674 label = "BootLoader(NAND)"; 675 reg = <0x80000 0x200000>; 676 }; 677 partition@280000 { 678 label = "Kernel zImage(NAND)"; 679 reg = <0x280000 0x300000>; 680 }; 681 partition@580000 { 682 label = "Root Filesystem(NAND)"; 683 reg = <0x580000 0x1600000>; 684 }; 685 partition@1b80000 { 686 label = "User Filesystem(NAND)"; 687 reg = <0x1b80000 0x6480000>; 688 }; 689 }; 690 691 /* I2C0 connected to the STw4811 power management chip */ 692 i2c0 { 693 compatible = "st,nomadik-i2c", "arm,primecell"; 694 reg = <0x101f8000 0x1000>; 695 interrupt-parent = <&vica>; 696 interrupts = <20>; 697 clock-frequency = <100000>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 clocks = <&i2c0clk>, <&pclki2c0>; 701 clock-names = "mclk", "apb_pclk"; 702 pinctrl-names = "default"; 703 pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>; 704 705 stw4811@2d { 706 compatible = "st,stw4811"; 707 reg = <0x2d>; 708 vmmc_regulator: vmmc { 709 compatible = "st,stw481x-vmmc"; 710 regulator-name = "VMMC"; 711 regulator-min-microvolt = <1800000>; 712 regulator-max-microvolt = <3300000>; 713 }; 714 }; 715 }; 716 717 /* I2C1 connected to various sensors */ 718 i2c1 { 719 compatible = "st,nomadik-i2c", "arm,primecell"; 720 reg = <0x101f7000 0x1000>; 721 interrupt-parent = <&vica>; 722 interrupts = <21>; 723 clock-frequency = <100000>; 724 #address-cells = <1>; 725 #size-cells = <0>; 726 clocks = <&i2c1clk>, <&pclki2c1>; 727 clock-names = "mclk", "apb_pclk"; 728 pinctrl-names = "default"; 729 pinctrl-0 = <&i2c1_default_mux>, <&i2c1_default_mode>; 730 731 camera@2d { 732 compatible = "st,camera"; 733 reg = <0x10>; 734 }; 735 stw5095@1a { 736 compatible = "st,stw5095"; 737 reg = <0x1a>; 738 }; 739 }; 740 741 amba { 742 compatible = "simple-bus"; 743 #address-cells = <1>; 744 #size-cells = <1>; 745 ranges; 746 747 clcd@10120000 { 748 compatible = "arm,pl110", "arm,primecell"; 749 reg = <0x10120000 0x1000>; 750 interrupt-names = "combined"; 751 interrupts = <14>; 752 interrupt-parent = <&vica>; 753 clocks = <&clcdclk>, <&hclkclcd>; 754 clock-names = "clcdclk", "apb_pclk"; 755 status = "disabled"; 756 }; 757 758 vica: interrupt-controller@10140000 { 759 compatible = "arm,versatile-vic"; 760 interrupt-controller; 761 #interrupt-cells = <1>; 762 reg = <0x10140000 0x20>; 763 }; 764 765 vicb: interrupt-controller@10140020 { 766 compatible = "arm,versatile-vic"; 767 interrupt-controller; 768 #interrupt-cells = <1>; 769 reg = <0x10140020 0x20>; 770 }; 771 772 uart0: uart@101fd000 { 773 compatible = "arm,pl011", "arm,primecell"; 774 reg = <0x101fd000 0x1000>; 775 interrupt-parent = <&vica>; 776 interrupts = <12>; 777 clocks = <&uart0clk>, <&pclkuart0>; 778 clock-names = "uartclk", "apb_pclk"; 779 status = "disabled"; 780 dmas = <&dmac0 14 1>, 781 <&dmac0 15 1>; 782 dma-names = "rx", "tx"; 783 }; 784 785 uart1: uart@101fb000 { 786 compatible = "arm,pl011", "arm,primecell"; 787 reg = <0x101fb000 0x1000>; 788 interrupt-parent = <&vica>; 789 interrupts = <17>; 790 clocks = <&uart1clk>, <&pclkuart1>; 791 clock-names = "uartclk", "apb_pclk"; 792 pinctrl-names = "default"; 793 pinctrl-0 = <&uart1_default_mux>; 794 dmas = <&dmac1 22 1>, 795 <&dmac1 23 1>; 796 dma-names = "rx", "tx"; 797 }; 798 799 uart2: uart@101f2000 { 800 compatible = "arm,pl011", "arm,primecell"; 801 reg = <0x101f2000 0x1000>; 802 interrupt-parent = <&vica>; 803 interrupts = <28>; 804 clocks = <&uart2clk>, <&pclkuart2>; 805 clock-names = "uartclk", "apb_pclk"; 806 status = "disabled"; 807 dmas = <&dmac1 30 1>, 808 <&dmac1 31 1>; 809 dma-names = "rx", "tx"; 810 }; 811 812 rng: rng@101b0000 { 813 compatible = "arm,primecell"; 814 reg = <0x101b0000 0x1000>; 815 clocks = <&rngcclk>, <&hclkrng>; 816 clock-names = "rng", "apb_pclk"; 817 }; 818 819 rtc: rtc@101e8000 { 820 compatible = "arm,pl031", "arm,primecell"; 821 reg = <0x101e8000 0x1000>; 822 clocks = <&pclk>; 823 clock-names = "apb_pclk"; 824 interrupt-parent = <&vica>; 825 interrupts = <10>; 826 }; 827 828 mmcsd: mmc@101f6000 { 829 compatible = "arm,pl18x", "arm,primecell"; 830 reg = <0x101f6000 0x1000>; 831 clocks = <&sdiclk>, <&pclksdi>; 832 clock-names = "mclk", "apb_pclk"; 833 interrupt-parent = <&vica>; 834 interrupts = <22>; 835 max-frequency = <400000>; 836 bus-width = <4>; 837 cap-mmc-highspeed; 838 cap-sd-highspeed; 839 full-pwr-cycle; 840 /* 841 * The STw4811 circuit used with the Nomadik strictly 842 * requires that all of these signal direction pins be 843 * routed and used for its 4-bit levelshifter. 844 */ 845 st,sig-dir-dat0; 846 st,sig-dir-dat2; 847 st,sig-dir-dat31; 848 st,sig-dir-cmd; 849 st,sig-pin-fbclk; 850 pinctrl-names = "default"; 851 pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; 852 vmmc-supply = <&vmmc_regulator>; 853 }; 854 855 dmac0: dma-controller@10130000 { 856 compatible = "arm,pl080", "arm,primecell"; 857 reg = <0x10130000 0x1000>; 858 interrupt-parent = <&vica>; 859 interrupts = <15>; 860 clocks = <&hclkdma0>; 861 clock-names = "apb_pclk"; 862 lli-bus-interface-ahb1; 863 lli-bus-interface-ahb2; 864 mem-bus-interface-ahb2; 865 memcpy-burst-size = <256>; 866 memcpy-bus-width = <32>; 867 #dma-cells = <2>; 868 }; 869 dmac1: dma-controller@10150000 { 870 compatible = "arm,pl080", "arm,primecell"; 871 reg = <0x10150000 0x1000>; 872 interrupt-parent = <&vica>; 873 interrupts = <13>; 874 clocks = <&hclkdma1>; 875 clock-names = "apb_pclk"; 876 lli-bus-interface-ahb1; 877 lli-bus-interface-ahb2; 878 mem-bus-interface-ahb2; 879 memcpy-burst-size = <256>; 880 memcpy-bus-width = <32>; 881 #dma-cells = <2>; 882 }; 883 }; 884};