cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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stm32f429-disco.dts (5885B)


      1/*
      2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
      3 *
      4 * This file is dual-licensed: you can use it either under the terms
      5 * of the GPL or the X11 license, at your option. Note that this dual
      6 * licensing only applies to this file, and not this project as a
      7 * whole.
      8 *
      9 *  a) This file is free software; you can redistribute it and/or
     10 *     modify it under the terms of the GNU General Public License as
     11 *     published by the Free Software Foundation; either version 2 of the
     12 *     License, or (at your option) any later version.
     13 *
     14 *     This file is distributed in the hope that it will be useful,
     15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
     16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     17 *     GNU General Public License for more details.
     18 *
     19 *     You should have received a copy of the GNU General Public
     20 *     License along with this file; if not, write to the Free
     21 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
     22 *     MA 02110-1301 USA
     23 *
     24 * Or, alternatively,
     25 *
     26 *  b) Permission is hereby granted, free of charge, to any person
     27 *     obtaining a copy of this software and associated documentation
     28 *     files (the "Software"), to deal in the Software without
     29 *     restriction, including without limitation the rights to use,
     30 *     copy, modify, merge, publish, distribute, sublicense, and/or
     31 *     sell copies of the Software, and to permit persons to whom the
     32 *     Software is furnished to do so, subject to the following
     33 *     conditions:
     34 *
     35 *     The above copyright notice and this permission notice shall be
     36 *     included in all copies or substantial portions of the Software.
     37 *
     38 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     39 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
     40 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     41 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
     42 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
     43 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     44 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     45 *     OTHER DEALINGS IN THE SOFTWARE.
     46 */
     47
     48/dts-v1/;
     49#include "stm32f429.dtsi"
     50#include "stm32f429-pinctrl.dtsi"
     51#include <dt-bindings/input/input.h>
     52#include <dt-bindings/interrupt-controller/irq.h>
     53#include <dt-bindings/gpio/gpio.h>
     54
     55/ {
     56	model = "STMicroelectronics STM32F429i-DISCO board";
     57	compatible = "st,stm32f429i-disco", "st,stm32f429";
     58
     59	chosen {
     60		bootargs = "root=/dev/ram";
     61		stdout-path = "serial0:115200n8";
     62	};
     63
     64	memory@90000000 {
     65		device_type = "memory";
     66		reg = <0x90000000 0x800000>;
     67	};
     68
     69	aliases {
     70		serial0 = &usart1;
     71	};
     72
     73	leds {
     74		compatible = "gpio-leds";
     75		led-red {
     76			gpios = <&gpiog 14 0>;
     77		};
     78		led-green {
     79			gpios = <&gpiog 13 0>;
     80			linux,default-trigger = "heartbeat";
     81		};
     82	};
     83
     84	gpio-keys {
     85		compatible = "gpio-keys";
     86		autorepeat;
     87		button-0 {
     88			label = "User";
     89			linux,code = <KEY_HOME>;
     90			gpios = <&gpioa 0 0>;
     91		};
     92	};
     93
     94	/* This turns on vbus for otg for host mode (dwc2) */
     95	vcc5v_otg: vcc5v-otg-regulator {
     96		compatible = "regulator-fixed";
     97		gpio = <&gpioc 4 0>;
     98		regulator-name = "vcc5_host1";
     99		regulator-always-on;
    100	};
    101};
    102
    103&clk_hse {
    104	clock-frequency = <8000000>;
    105};
    106
    107&crc {
    108	status = "okay";
    109};
    110
    111&i2c3 {
    112	pinctrl-names = "default";
    113	pinctrl-0 = <&i2c3_pins>;
    114	clock-frequency = <100000>;
    115	status = "okay";
    116
    117	stmpe811@41 {
    118		compatible = "st,stmpe811";
    119		reg = <0x41>;
    120		interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
    121		interrupt-parent = <&gpioa>;
    122		/* 3.25 MHz ADC clock speed */
    123		st,adc-freq = <1>;
    124		/* 12-bit ADC */
    125		st,mod-12b = <1>;
    126		/* internal ADC reference */
    127		st,ref-sel = <0>;
    128		/* ADC converstion time: 80 clocks */
    129		st,sample-time = <4>;
    130
    131		stmpe_touchscreen {
    132			compatible = "st,stmpe-ts";
    133			/* 8 sample average control */
    134			st,ave-ctrl = <3>;
    135			/* 7 length fractional part in z */
    136			st,fraction-z = <7>;
    137			/*
    138			 * 50 mA typical 80 mA max touchscreen drivers
    139			 * current limit value
    140			 */
    141			st,i-drive = <1>;
    142			/* 1 ms panel driver settling time */
    143			st,settling = <3>;
    144			/* 5 ms touch detect interrupt delay */
    145			st,touch-det-delay = <5>;
    146		};
    147
    148		stmpe_adc {
    149			compatible = "st,stmpe-adc";
    150			/* forbid to use ADC channels 3-0 (touch) */
    151			st,norequest-mask = <0x0F>;
    152		};
    153	};
    154};
    155
    156&ltdc {
    157	status = "okay";
    158	pinctrl-0 = <&ltdc_pins_b>;
    159	pinctrl-names = "default";
    160
    161	port {
    162		ltdc_out_rgb: endpoint {
    163			remote-endpoint = <&panel_in_rgb>;
    164		};
    165	};
    166};
    167
    168&rtc {
    169	assigned-clocks = <&rcc 1 CLK_RTC>;
    170	assigned-clock-parents = <&rcc 1 CLK_LSI>;
    171	status = "okay";
    172};
    173
    174&spi5 {
    175	status = "okay";
    176	pinctrl-0 = <&spi5_pins>;
    177	pinctrl-names = "default";
    178	#address-cells = <1>;
    179	#size-cells = <0>;
    180	cs-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>, <&gpioc 2 GPIO_ACTIVE_LOW>;
    181
    182	l3gd20: l3gd20@0 {
    183		compatible = "st,l3gd20-gyro";
    184		spi-max-frequency = <10000000>;
    185		st,drdy-int-pin = <2>;
    186		interrupt-parent = <&gpioa>;
    187		interrupts = <1 IRQ_TYPE_EDGE_RISING>,
    188				<2 IRQ_TYPE_EDGE_RISING>;
    189		reg = <0>;
    190		status = "okay";
    191	};
    192
    193	display: display@1{
    194		/* Connect panel-ilitek-9341 to ltdc */
    195		compatible = "st,sf-tc240t-9370-t", "ilitek,ili9341";
    196		reg = <1>;
    197		spi-3wire;
    198		spi-max-frequency = <10000000>;
    199		dc-gpios = <&gpiod 13 0>;
    200		port {
    201			panel_in_rgb: endpoint {
    202			remote-endpoint = <&ltdc_out_rgb>;
    203			};
    204		};
    205	};
    206};
    207
    208&timers5 {
    209	/* Override timer5 to act as clockevent */
    210	compatible = "st,stm32-timer";
    211	interrupts = <50>;
    212	status = "okay";
    213	/delete-property/#address-cells;
    214	/delete-property/#size-cells;
    215	/delete-property/clock-names;
    216	/delete-node/pwm;
    217	/delete-node/timer@4;
    218};
    219
    220&usart1 {
    221	pinctrl-0 = <&usart1_pins_a>;
    222	pinctrl-names = "default";
    223	status = "okay";
    224};
    225
    226&usbotg_hs {
    227	compatible = "st,stm32f4x9-fsotg";
    228	dr_mode = "host";
    229	pinctrl-0 = <&usbotg_fs_pins_b>;
    230	pinctrl-names = "default";
    231	status = "okay";
    232};