cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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stm32h743i-eval.dts (4188B)

      1/*
      2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
      3 *
      4 * This file is dual-licensed: you can use it either under the terms
      5 * of the GPL or the X11 license, at your option. Note that this dual
      6 * licensing only applies to this file, and not this project as a
      7 * whole.
      8 *
      9 *  a) This file is free software; you can redistribute it and/or
     10 *     modify it under the terms of the GNU General Public License as
     11 *     published by the Free Software Foundation; either version 2 of the
     12 *     License, or (at your option) any later version.
     13 *
     14 *     This file is distributed in the hope that it will be useful,
     15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
     16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     17 *     GNU General Public License for more details.
     18 *
     19 * Or, alternatively,
     20 *
     21 *  b) Permission is hereby granted, free of charge, to any person
     22 *     obtaining a copy of this software and associated documentation
     23 *     files (the "Software"), to deal in the Software without
     24 *     restriction, including without limitation the rights to use,
     25 *     copy, modify, merge, publish, distribute, sublicense, and/or
     26 *     sell copies of the Software, and to permit persons to whom the
     27 *     Software is furnished to do so, subject to the following
     28 *     conditions:
     29 *
     30 *     The above copyright notice and this permission notice shall be
     31 *     included in all copies or substantial portions of the Software.
     32 *
     33 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     34 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
     35 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     36 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
     37 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
     38 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     39 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     40 *     OTHER DEALINGS IN THE SOFTWARE.
     41 */
     42
     43/dts-v1/;
     44#include "stm32h743.dtsi"
     45#include "stm32h7-pinctrl.dtsi"
     46
     47/ {
     48	model = "STMicroelectronics STM32H743i-EVAL board";
     49	compatible = "st,stm32h743i-eval", "st,stm32h743";
     50
     51	chosen {
     52		bootargs = "root=/dev/ram";
     53		stdout-path = "serial0:115200n8";
     54	};
     55
     56	memory@d0000000 {
     57		device_type = "memory";
     58		reg = <0xd0000000 0x2000000>;
     59	};
     60
     61	aliases {
     62		serial0 = &usart1;
     63	};
     64
     65	vdda: regulator-vdda {
     66		compatible = "regulator-fixed";
     67		regulator-name = "vdda";
     68		regulator-min-microvolt = <3300000>;
     69		regulator-max-microvolt = <3300000>;
     70		regulator-always-on;
     71	};
     72
     73	v2v9_sd: regulator-v2v9_sd {
     74		compatible = "regulator-fixed";
     75		regulator-name = "v2v9_sd";
     76		regulator-min-microvolt = <2900000>;
     77		regulator-max-microvolt = <2900000>;
     78		regulator-always-on;
     79	};
     80
     81	usbotg_hs_phy: usb-phy {
     82		#phy-cells = <0>;
     83		compatible = "usb-nop-xceiv";
     84		clocks = <&rcc USB1ULPI_CK>;
     85		clock-names = "main_clk";
     86	};
     87};
     88
     89&adc_12 {
     90	vdda-supply = <&vdda>;
     91	vref-supply = <&vdda>;
     92	status = "okay";
     93	adc1: adc@0 {
     94		/* potentiometer */
     95		st,adc-channels = <0>;
     96		status = "okay";
     97	};
     98};
     99
    100&clk_hse {
    101	clock-frequency = <25000000>;
    102};
    103
    104&i2c1 {
    105	pinctrl-0 = <&i2c1_pins_a>;
    106	pinctrl-names = "default";
    107	i2c-scl-rising-time-ns = <185>;
    108	i2c-scl-falling-time-ns = <20>;
    109	status = "okay";
    110};
    111
    112&rtc {
    113	status = "okay";
    114};
    115
    116&mac {
    117	status = "disabled";
    118	pinctrl-0	= <&ethernet_rmii>;
    119	pinctrl-names	= "default";
    120	phy-mode	= "rmii";
    121	phy-handle	= <&phy0>;
    122
    123	mdio0 {
    124		#address-cells = <1>;
    125		#size-cells = <0>;
    126		compatible = "snps,dwmac-mdio";
    127		phy0: ethernet-phy@0 {
    128			reg = <0>;
    129		};
    130	};
    131};
    132
    133&sdmmc1 {
    134	pinctrl-names = "default", "opendrain", "sleep";
    135	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
    136	pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
    137	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
    138	broken-cd;
    139	st,sig-dir;
    140	st,neg-edge;
    141	st,use-ckin;
    142	bus-width = <4>;
    143	vmmc-supply = <&v2v9_sd>;
    144	status = "okay";
    145};
    146
    147&usart1 {
    148	pinctrl-0 = <&usart1_pins>;
    149	pinctrl-names = "default";
    150	status = "okay";
    151};
    152
    153&usbotg_hs {
    154	pinctrl-0 = <&usbotg_hs_pins_a>;
    155	pinctrl-names = "default";
    156	phys = <&usbotg_hs_phy>;
    157	phy-names = "usb2-phy";
    158	dr_mode = "otg";
    159	status = "okay";
    160};