stm32mp131.dtsi (8868B)
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7 8/ { 9 #address-cells = <1>; 10 #size-cells = <1>; 11 12 cpus { 13 #address-cells = <1>; 14 #size-cells = <0>; 15 16 cpu0: cpu@0 { 17 compatible = "arm,cortex-a7"; 18 device_type = "cpu"; 19 reg = <0>; 20 }; 21 }; 22 23 arm-pmu { 24 compatible = "arm,cortex-a7-pmu"; 25 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 26 interrupt-affinity = <&cpu0>; 27 interrupt-parent = <&intc>; 28 }; 29 30 clocks { 31 clk_axi: clk-axi { 32 #clock-cells = <0>; 33 compatible = "fixed-clock"; 34 clock-frequency = <266500000>; 35 }; 36 37 clk_hse: clk-hse { 38 #clock-cells = <0>; 39 compatible = "fixed-clock"; 40 clock-frequency = <24000000>; 41 }; 42 43 clk_hsi: clk-hsi { 44 #clock-cells = <0>; 45 compatible = "fixed-clock"; 46 clock-frequency = <64000000>; 47 }; 48 49 clk_lsi: clk-lsi { 50 #clock-cells = <0>; 51 compatible = "fixed-clock"; 52 clock-frequency = <32000>; 53 }; 54 55 clk_pclk3: clk-pclk3 { 56 #clock-cells = <0>; 57 compatible = "fixed-clock"; 58 clock-frequency = <104438965>; 59 }; 60 61 clk_pclk4: clk-pclk4 { 62 #clock-cells = <0>; 63 compatible = "fixed-clock"; 64 clock-frequency = <133250000>; 65 }; 66 67 clk_pll4_p: clk-pll4_p { 68 #clock-cells = <0>; 69 compatible = "fixed-clock"; 70 clock-frequency = <50000000>; 71 }; 72 73 clk_pll4_r: clk-pll4_r { 74 #clock-cells = <0>; 75 compatible = "fixed-clock"; 76 clock-frequency = <99000000>; 77 }; 78 79 clk_rtc_k: clk-rtc-k { 80 #clock-cells = <0>; 81 compatible = "fixed-clock"; 82 clock-frequency = <32768>; 83 }; 84 }; 85 86 intc: interrupt-controller@a0021000 { 87 compatible = "arm,cortex-a7-gic"; 88 #interrupt-cells = <3>; 89 interrupt-controller; 90 reg = <0xa0021000 0x1000>, 91 <0xa0022000 0x2000>; 92 }; 93 94 psci { 95 compatible = "arm,psci-1.0"; 96 method = "smc"; 97 }; 98 99 timer { 100 compatible = "arm,armv7-timer"; 101 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 103 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 104 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 105 interrupt-parent = <&intc>; 106 always-on; 107 }; 108 109 soc { 110 compatible = "simple-bus"; 111 #address-cells = <1>; 112 #size-cells = <1>; 113 interrupt-parent = <&intc>; 114 ranges; 115 116 uart4: serial@40010000 { 117 compatible = "st,stm32h7-uart"; 118 reg = <0x40010000 0x400>; 119 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 120 clocks = <&clk_hsi>; 121 status = "disabled"; 122 }; 123 124 dma1: dma-controller@48000000 { 125 compatible = "st,stm32-dma"; 126 reg = <0x48000000 0x400>; 127 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&clk_pclk4>; 136 #dma-cells = <4>; 137 st,mem2mem; 138 dma-requests = <8>; 139 }; 140 141 dma2: dma-controller@48001000 { 142 compatible = "st,stm32-dma"; 143 reg = <0x48001000 0x400>; 144 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 152 clocks = <&clk_pclk4>; 153 #dma-cells = <4>; 154 st,mem2mem; 155 dma-requests = <8>; 156 }; 157 158 dmamux1: dma-router@48002000 { 159 compatible = "st,stm32h7-dmamux"; 160 reg = <0x48002000 0x40>; 161 clocks = <&clk_pclk4>; 162 #dma-cells = <3>; 163 dma-masters = <&dma1 &dma2>; 164 dma-requests = <128>; 165 dma-channels = <16>; 166 }; 167 168 exti: interrupt-controller@5000d000 { 169 compatible = "st,stm32mp13-exti", "syscon"; 170 interrupt-controller; 171 #interrupt-cells = <2>; 172 reg = <0x5000d000 0x400>; 173 }; 174 175 syscfg: syscon@50020000 { 176 compatible = "st,stm32mp157-syscfg", "syscon"; 177 reg = <0x50020000 0x400>; 178 clocks = <&clk_pclk3>; 179 }; 180 181 mdma: dma-controller@58000000 { 182 compatible = "st,stm32h7-mdma"; 183 reg = <0x58000000 0x1000>; 184 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&clk_pclk4>; 186 #dma-cells = <5>; 187 dma-channels = <32>; 188 dma-requests = <48>; 189 }; 190 191 sdmmc1: mmc@58005000 { 192 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 193 arm,primecell-periphid = <0x20253180>; 194 reg = <0x58005000 0x1000>, <0x58006000 0x1000>; 195 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 196 interrupt-names = "cmd_irq"; 197 clocks = <&clk_pll4_p>; 198 clock-names = "apb_pclk"; 199 cap-sd-highspeed; 200 cap-mmc-highspeed; 201 max-frequency = <130000000>; 202 status = "disabled"; 203 }; 204 205 sdmmc2: mmc@58007000 { 206 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 207 arm,primecell-periphid = <0x20253180>; 208 reg = <0x58007000 0x1000>, <0x58008000 0x1000>; 209 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 210 interrupt-names = "cmd_irq"; 211 clocks = <&clk_pll4_p>; 212 clock-names = "apb_pclk"; 213 cap-sd-highspeed; 214 cap-mmc-highspeed; 215 max-frequency = <130000000>; 216 status = "disabled"; 217 }; 218 219 iwdg2: watchdog@5a002000 { 220 compatible = "st,stm32mp1-iwdg"; 221 reg = <0x5a002000 0x400>; 222 clocks = <&clk_pclk4>, <&clk_lsi>; 223 clock-names = "pclk", "lsi"; 224 status = "disabled"; 225 }; 226 227 rtc: rtc@5c004000 { 228 compatible = "st,stm32mp1-rtc"; 229 reg = <0x5c004000 0x400>; 230 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&clk_pclk4>, <&clk_rtc_k>; 232 clock-names = "pclk", "rtc_ck"; 233 status = "disabled"; 234 }; 235 236 bsec: efuse@5c005000 { 237 compatible = "st,stm32mp15-bsec"; 238 reg = <0x5c005000 0x400>; 239 #address-cells = <1>; 240 #size-cells = <1>; 241 242 part_number_otp: part_number_otp@4 { 243 reg = <0x4 0x2>; 244 }; 245 ts_cal1: calib@5c { 246 reg = <0x5c 0x2>; 247 }; 248 ts_cal2: calib@5e { 249 reg = <0x5e 0x2>; 250 }; 251 }; 252 253 /* 254 * Break node order to solve dependency probe issue between 255 * pinctrl and exti. 256 */ 257 pinctrl: pinctrl@50002000 { 258 #address-cells = <1>; 259 #size-cells = <1>; 260 compatible = "st,stm32mp135-pinctrl"; 261 ranges = <0 0x50002000 0x8400>; 262 interrupt-parent = <&exti>; 263 st,syscfg = <&exti 0x60 0xff>; 264 pins-are-numbered; 265 266 gpioa: gpio@50002000 { 267 gpio-controller; 268 #gpio-cells = <2>; 269 interrupt-controller; 270 #interrupt-cells = <2>; 271 reg = <0x0 0x400>; 272 clocks = <&clk_pclk4>; 273 st,bank-name = "GPIOA"; 274 ngpios = <16>; 275 gpio-ranges = <&pinctrl 0 0 16>; 276 }; 277 278 gpiob: gpio@50003000 { 279 gpio-controller; 280 #gpio-cells = <2>; 281 interrupt-controller; 282 #interrupt-cells = <2>; 283 reg = <0x1000 0x400>; 284 clocks = <&clk_pclk4>; 285 st,bank-name = "GPIOB"; 286 ngpios = <16>; 287 gpio-ranges = <&pinctrl 0 16 16>; 288 }; 289 290 gpioc: gpio@50004000 { 291 gpio-controller; 292 #gpio-cells = <2>; 293 interrupt-controller; 294 #interrupt-cells = <2>; 295 reg = <0x2000 0x400>; 296 clocks = <&clk_pclk4>; 297 st,bank-name = "GPIOC"; 298 ngpios = <16>; 299 gpio-ranges = <&pinctrl 0 32 16>; 300 }; 301 302 gpiod: gpio@50005000 { 303 gpio-controller; 304 #gpio-cells = <2>; 305 interrupt-controller; 306 #interrupt-cells = <2>; 307 reg = <0x3000 0x400>; 308 clocks = <&clk_pclk4>; 309 st,bank-name = "GPIOD"; 310 ngpios = <16>; 311 gpio-ranges = <&pinctrl 0 48 16>; 312 }; 313 314 gpioe: gpio@50006000 { 315 gpio-controller; 316 #gpio-cells = <2>; 317 interrupt-controller; 318 #interrupt-cells = <2>; 319 reg = <0x4000 0x400>; 320 clocks = <&clk_pclk4>; 321 st,bank-name = "GPIOE"; 322 ngpios = <16>; 323 gpio-ranges = <&pinctrl 0 64 16>; 324 }; 325 326 gpiof: gpio@50007000 { 327 gpio-controller; 328 #gpio-cells = <2>; 329 interrupt-controller; 330 #interrupt-cells = <2>; 331 reg = <0x5000 0x400>; 332 clocks = <&clk_pclk4>; 333 st,bank-name = "GPIOF"; 334 ngpios = <16>; 335 gpio-ranges = <&pinctrl 0 80 16>; 336 }; 337 338 gpiog: gpio@50008000 { 339 gpio-controller; 340 #gpio-cells = <2>; 341 interrupt-controller; 342 #interrupt-cells = <2>; 343 reg = <0x6000 0x400>; 344 clocks = <&clk_pclk4>; 345 st,bank-name = "GPIOG"; 346 ngpios = <16>; 347 gpio-ranges = <&pinctrl 0 96 16>; 348 }; 349 350 gpioh: gpio@50009000 { 351 gpio-controller; 352 #gpio-cells = <2>; 353 interrupt-controller; 354 #interrupt-cells = <2>; 355 reg = <0x7000 0x400>; 356 clocks = <&clk_pclk4>; 357 st,bank-name = "GPIOH"; 358 ngpios = <15>; 359 gpio-ranges = <&pinctrl 0 112 15>; 360 }; 361 362 gpioi: gpio@5000a000 { 363 gpio-controller; 364 #gpio-cells = <2>; 365 interrupt-controller; 366 #interrupt-cells = <2>; 367 reg = <0x8000 0x400>; 368 clocks = <&clk_pclk4>; 369 st,bank-name = "GPIOI"; 370 ngpios = <8>; 371 gpio-ranges = <&pinctrl 0 128 8>; 372 }; 373 }; 374 }; 375};