cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

stm32mp157a-dhcor-avenger96.dts (983B)


      1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
      2/*
      3 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
      4 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
      5 * Copyright (C) 2020 Marek Vasut <marex@denx.de>
      6 *
      7 * DHCOR STM32MP1 variant:
      8 * DHCR-STM32MP157A-C065-R102-V18-SPI-C-01LG
      9 * DHCOR PCB number: 586-100 or newer
     10 * Avenger96 PCB number: 588-200 or newer
     11 */
     12
     13/dts-v1/;
     14
     15#include "stm32mp157.dtsi"
     16#include "stm32mp15xc.dtsi"
     17#include "stm32mp15xx-dhcor-som.dtsi"
     18#include "stm32mp15xx-dhcor-avenger96.dtsi"
     19
     20/ {
     21	model = "Arrow Electronics STM32MP157A Avenger96 board";
     22	compatible = "arrow,stm32mp157a-avenger96", "dh,stm32mp157a-dhcor-som",
     23		     "st,stm32mp157";
     24};
     25
     26&m_can1 {
     27	pinctrl-names = "default", "sleep";
     28	pinctrl-0 = <&m_can1_pins_b>;
     29	pinctrl-1 = <&m_can1_sleep_pins_b>;
     30	status = "disabled";
     31};
     32
     33&m_can2 {
     34	pinctrl-names = "default", "sleep";
     35	pinctrl-0 = <&m_can2_pins_a>;
     36	pinctrl-1 = <&m_can2_sleep_pins_a>;
     37	status = "disabled";
     38};