cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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stm32mp157a-icore-stm32mp1-ctouch2-of10.dts (2409B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
      2/*
      3 * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
      4 * Copyright (c) 2020 Engicam srl
      5 * Copyright (c) 2020 Amarula Solutons(India)
      6 */
      7
      8/dts-v1/;
      9#include "stm32mp157.dtsi"
     10#include "stm32mp157a-icore-stm32mp1.dtsi"
     11#include "stm32mp15-pinctrl.dtsi"
     12#include "stm32mp15xxaa-pinctrl.dtsi"
     13#include <dt-bindings/gpio/gpio.h>
     14
     15/ {
     16	model = "Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1\" Open Frame";
     17	compatible = "engicam,icore-stm32mp1-ctouch2-of10",
     18		     "engicam,icore-stm32mp1", "st,stm32mp157";
     19
     20	aliases {
     21		serial0 = &uart4;
     22	};
     23
     24	backlight: backlight {
     25		compatible = "gpio-backlight";
     26		gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>;
     27		default-on;
     28	};
     29
     30	chosen {
     31		stdout-path = "serial0:115200n8";
     32	};
     33
     34	panel {
     35		compatible = "ampire,am-1280800n3tzqw-t00h";
     36		backlight = <&backlight>;
     37		power-supply = <&v3v3>;
     38
     39		port {
     40			panel_in_lvds: endpoint {
     41				remote-endpoint = <&bridge_out>;
     42			};
     43		};
     44	};
     45};
     46
     47&dsi {
     48	status = "okay";
     49	phy-dsi-supply = <&reg18>;
     50
     51	ports {
     52		port@0 {
     53			reg = <0>;
     54			dsi_in: endpoint {
     55				remote-endpoint = <&ltdc_ep0_out>;
     56			};
     57		};
     58
     59		port@1 {
     60			reg = <1>;
     61			dsi_out: endpoint {
     62				remote-endpoint = <&bridge_in>;
     63			};
     64		};
     65	};
     66};
     67
     68&i2c6 {
     69	i2c-scl-falling-time-ns = <20>;
     70	i2c-scl-rising-time-ns = <185>;
     71	pinctrl-names = "default", "sleep";
     72	pinctrl-0 = <&i2c6_pins_a>;
     73	pinctrl-1 = <&i2c6_sleep_pins_a>;
     74	status = "okay";
     75
     76	bridge@2c {
     77		compatible = "ti,sn65dsi84";
     78		reg = <0x2c>;
     79		enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>;
     80
     81		ports {
     82			#address-cells = <1>;
     83			#size-cells = <0>;
     84
     85			port@0 {
     86				reg = <0>;
     87				bridge_in: endpoint {
     88					remote-endpoint = <&dsi_out>;
     89					data-lanes = <1 2>;
     90				};
     91			};
     92
     93			port@2 {
     94				reg = <2>;
     95				bridge_out: endpoint {
     96					remote-endpoint = <&panel_in_lvds>;
     97				};
     98			};
     99		};
    100	};
    101};
    102
    103&ltdc {
    104	status = "okay";
    105
    106	port {
    107		ltdc_ep0_out: endpoint@0 {
    108			reg = <0>;
    109			remote-endpoint = <&dsi_in>;
    110		};
    111	};
    112};
    113
    114&sdmmc1 {
    115	bus-width = <4>;
    116	disable-wp;
    117	pinctrl-names = "default", "opendrain", "sleep";
    118	pinctrl-0 = <&sdmmc1_b4_pins_a>;
    119	pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
    120	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
    121	st,neg-edge;
    122	vmmc-supply = <&v3v3>;
    123	status = "okay";
    124};
    125
    126&uart4 {
    127	pinctrl-names = "default", "sleep", "idle";
    128	pinctrl-0 = <&uart4_pins_a>;
    129	pinctrl-1 = <&uart4_sleep_pins_a>;
    130	pinctrl-2 = <&uart4_idle_pins_a>;
    131	status = "okay";
    132};