cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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stm32mp157a-microgea-stm32mp1.dtsi (2822B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
      2/*
      3 * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
      4 * Copyright (c) 2020 Engicam srl
      5 * Copyright (c) 2020 Amarula Solutons(India)
      6 */
      7
      8/ {
      9	compatible = "engicam,microgea-stm32mp1", "st,stm32mp157";
     10
     11	memory@c0000000 {
     12		device_type = "memory";
     13		reg = <0xc0000000 0x10000000>;
     14	};
     15
     16	reserved-memory {
     17		#address-cells = <1>;
     18		#size-cells = <1>;
     19		ranges;
     20
     21		mcuram2: mcuram2@10000000 {
     22			compatible = "shared-dma-pool";
     23			reg = <0x10000000 0x40000>;
     24			no-map;
     25		};
     26
     27		vdev0vring0: vdev0vring0@10040000 {
     28			compatible = "shared-dma-pool";
     29			reg = <0x10040000 0x1000>;
     30			no-map;
     31		};
     32
     33		vdev0vring1: vdev0vring1@10041000 {
     34			compatible = "shared-dma-pool";
     35			reg = <0x10041000 0x1000>;
     36			no-map;
     37		};
     38
     39		vdev0buffer: vdev0buffer@10042000 {
     40			compatible = "shared-dma-pool";
     41			reg = <0x10042000 0x4000>;
     42			no-map;
     43		};
     44
     45		mcuram: mcuram@30000000 {
     46			compatible = "shared-dma-pool";
     47			reg = <0x30000000 0x40000>;
     48			no-map;
     49		};
     50
     51		retram: retram@38000000 {
     52			compatible = "shared-dma-pool";
     53			reg = <0x38000000 0x10000>;
     54			no-map;
     55		};
     56	};
     57
     58	vin: regulator-vin {
     59		compatible = "regulator-fixed";
     60		regulator-name = "vin";
     61		regulator-min-microvolt = <5000000>;
     62		regulator-max-microvolt = <5000000>;
     63		regulator-always-on;
     64	};
     65
     66	vddcore: regulator-vddcore {
     67		compatible = "regulator-fixed";
     68		regulator-name = "vddcore";
     69		regulator-min-microvolt = <1200000>;
     70		regulator-max-microvolt = <1200000>;
     71		regulator-always-on;
     72		vin-supply = <&vin>;
     73	};
     74
     75	vdd: regulator-vdd {
     76		compatible = "regulator-fixed";
     77		regulator-name = "vdd";
     78		regulator-min-microvolt = <3300000>;
     79		regulator-max-microvolt = <3300000>;
     80		regulator-always-on;
     81		vin-supply = <&vin>;
     82	};
     83
     84	vddq_ddr: regulator-vddq-ddr {
     85		compatible = "regulator-fixed";
     86		regulator-name = "vddq_ddr";
     87		regulator-min-microvolt = <1350000>;
     88		regulator-max-microvolt = <1350000>;
     89		regulator-always-on;
     90		vin-supply = <&vin>;
     91	};
     92};
     93
     94&dts {
     95	status = "okay";
     96};
     97
     98&fmc {
     99	pinctrl-names = "default", "sleep";
    100	pinctrl-0 = <&fmc_pins_a>;
    101	pinctrl-1 = <&fmc_sleep_pins_a>;
    102	status = "okay";
    103
    104	nand-controller@4,0 {
    105		status = "okay";
    106
    107		nand@0 {
    108			reg = <0>;
    109			nand-on-flash-bbt;
    110			#address-cells = <1>;
    111			#size-cells = <1>;
    112		};
    113	};
    114};
    115
    116&ipcc {
    117	status = "okay";
    118};
    119
    120&iwdg2{
    121	timeout-sec = <32>;
    122	status = "okay";
    123};
    124
    125&m4_rproc{
    126	memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
    127			<&vdev0vring1>, <&vdev0buffer>;
    128	mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
    129	mbox-names = "vq0", "vq1", "shutdown";
    130	interrupt-parent = <&exti>;
    131	interrupts = <68 1>;
    132	status = "okay";
    133};
    134
    135&rng1 {
    136	status = "okay";
    137};
    138
    139&rtc{
    140	status = "okay";
    141};
    142
    143&vrefbuf {
    144	regulator-min-microvolt = <2500000>;
    145	regulator-max-microvolt = <2500000>;
    146	vdda-supply = <&vdd>;
    147	status = "okay";
    148};