cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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stm32mp157c-dk2-scmi.dts (1633B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
      2/*
      3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
      4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
      5 */
      6
      7/dts-v1/;
      8
      9#include "stm32mp157c-dk2.dts"
     10#include "stm32mp15-scmi.dtsi"
     11
     12/ {
     13	model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board";
     14	compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157";
     15
     16	reserved-memory {
     17		optee@de000000 {
     18			reg = <0xde000000 0x2000000>;
     19			no-map;
     20		};
     21	};
     22};
     23
     24&cpu0 {
     25	clocks = <&scmi_clk CK_SCMI_MPU>;
     26};
     27
     28&cpu1 {
     29	clocks = <&scmi_clk CK_SCMI_MPU>;
     30};
     31
     32&cryp1 {
     33	clocks = <&scmi_clk CK_SCMI_CRYP1>;
     34	resets = <&scmi_reset RST_SCMI_CRYP1>;
     35};
     36
     37&dsi {
     38	phy-dsi-supply = <&scmi_reg18>;
     39	clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
     40};
     41
     42&gpioz {
     43	clocks = <&scmi_clk CK_SCMI_GPIOZ>;
     44};
     45
     46&hash1 {
     47	clocks = <&scmi_clk CK_SCMI_HASH1>;
     48	resets = <&scmi_reset RST_SCMI_HASH1>;
     49};
     50
     51&i2c4 {
     52	clocks = <&scmi_clk CK_SCMI_I2C4>;
     53	resets = <&scmi_reset RST_SCMI_I2C4>;
     54};
     55
     56&iwdg2 {
     57	clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
     58};
     59
     60&mdma1 {
     61	resets = <&scmi_reset RST_SCMI_MDMA>;
     62};
     63
     64&mlahb {
     65	resets = <&scmi_reset RST_SCMI_MCU>;
     66};
     67
     68&rcc {
     69	compatible = "st,stm32mp1-rcc-secure", "syscon";
     70	clock-names = "hse", "hsi", "csi", "lse", "lsi";
     71	clocks = <&scmi_clk CK_SCMI_HSE>,
     72		 <&scmi_clk CK_SCMI_HSI>,
     73		 <&scmi_clk CK_SCMI_CSI>,
     74		 <&scmi_clk CK_SCMI_LSE>,
     75		 <&scmi_clk CK_SCMI_LSI>;
     76};
     77
     78&rng1 {
     79	clocks = <&scmi_clk CK_SCMI_RNG1>;
     80	resets = <&scmi_reset RST_SCMI_RNG1>;
     81};
     82
     83&rtc {
     84	clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
     85};