cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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stm32mp157c-odyssey.dts (1966B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
      2/*
      3 * Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com>.
      4 */
      5
      6/dts-v1/;
      7
      8#include "stm32mp157c-odyssey-som.dtsi"
      9
     10/ {
     11	model = "Seeed Studio Odyssey-STM32MP157C Board";
     12	compatible = "seeed,stm32mp157c-odyssey",
     13		     "seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
     14
     15	aliases {
     16		ethernet0 = &ethernet0;
     17		serial0 = &uart4;
     18	};
     19
     20	chosen {
     21		stdout-path = "serial0:115200n8";
     22	};
     23};
     24
     25&dcmi {
     26	pinctrl-names = "default", "sleep";
     27	pinctrl-0 = <&dcmi_pins_b>;
     28	pinctrl-1 = <&dcmi_sleep_pins_b>;
     29};
     30
     31&ethernet0 {
     32	status = "okay";
     33	pinctrl-0 = <&ethernet0_rgmii_pins_a>;
     34	pinctrl-1 = <&ethernet0_rgmii_sleep_pins_a>;
     35	pinctrl-names = "default", "sleep";
     36	phy-mode = "rgmii-id";
     37	max-speed = <1000>;
     38	phy-handle = <&phy0>;
     39	assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>;
     40	assigned-clock-parents = <&rcc PLL4_P>;
     41	assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */
     42	st,eth-clk-sel;
     43
     44	mdio0 {
     45		#address-cells = <1>;
     46		#size-cells = <0>;
     47		compatible = "snps,dwmac-mdio";
     48		phy0: ethernet-phy@7 { /* KSZ9031RN */
     49			reg = <7>;
     50			reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */
     51			reset-assert-us = <10000>;
     52			reset-deassert-us = <300>;
     53		};
     54	};
     55};
     56
     57&i2c1 {
     58	pinctrl-names = "default", "sleep";
     59	pinctrl-0 = <&i2c1_pins_a>;
     60	pinctrl-1 = <&i2c1_sleep_pins_a>;
     61	i2c-scl-rising-time-ns = <100>;
     62	i2c-scl-falling-time-ns = <7>;
     63	status = "okay";
     64	/delete-property/dmas;
     65	/delete-property/dma-names;
     66};
     67
     68&sdmmc1 {
     69	pinctrl-names = "default", "opendrain", "sleep";
     70	pinctrl-0 = <&sdmmc1_b4_pins_a>;
     71	pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
     72	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
     73	cd-gpios = <&gpioi 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
     74	disable-wp;
     75	st,neg-edge;
     76	bus-width = <4>;
     77	vmmc-supply = <&v3v3>;
     78	status = "okay";
     79};
     80
     81&uart4 {
     82	pinctrl-names = "default";
     83	pinctrl-0 = <&uart4_pins_a>;
     84	/delete-property/dmas;
     85	/delete-property/dma-names;
     86	status = "okay";
     87};
     88