cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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stm32mp15xx-dhcom-drc02.dtsi (3376B)

      1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
      2/*
      3 * Copyright (C) 2020 Marek Vasut <marex@denx.de>
      4 */
      5
      6#include <dt-bindings/input/input.h>
      7#include <dt-bindings/pwm/pwm.h>
      8
      9/ {
     10	aliases {
     11		serial0 = &uart4;
     12		serial1 = &usart3;
     13		serial2 = &uart8;
     14	};
     15
     16	chosen {
     17		stdout-path = "serial0:115200n8";
     18	};
     19};
     20
     21&adc {
     22	status = "disabled";
     23};
     24
     25&dac {
     26	status = "disabled";
     27};
     28
     29&gpiob {
     30	/*
     31	 * NOTE: On DRC02, the RS485_RX_En is controlled by a separate
     32	 * GPIO line, however the STM32 UART driver assumes RX happens
     33	 * during TX anyway and that it only controls drive enable DE
     34	 * line. Hence, the RX is always enabled here.
     35	 */
     36	rs485-rx-en-hog {
     37		gpio-hog;
     38		gpios = <8 0>;
     39		output-low;
     40		line-name = "rs485-rx-en";
     41	};
     42};
     43
     44&gpiod {
     45	gpio-line-names = "", "", "", "",
     46			  "", "", "DHCOM-B", "",
     47			  "", "", "", "DRC02-Out1",
     48			  "DRC02-Out2", "", "", "";
     49};
     50
     51&gpioi {
     52	gpio-line-names = "DRC02-In1", "DHCOM-O", "DHCOM-H", "DHCOM-I",
     53			  "DHCOM-R", "DHCOM-M", "", "",
     54			  "DRC02-In2", "", "", "",
     55			  "", "", "", "";
     56
     57	/*
     58	 * NOTE: The USB Hub on the DRC02 needs a reset signal to be
     59	 * pulled high in order to be detected by the USB Controller.
     60	 * This signal should be handled by USB power sequencing in
     61	 * order to reset the Hub when USB bus is powered down, but
     62	 * so far there is no such functionality.
     63	 */
     64	usb-hub-hog {
     65		gpio-hog;
     66		gpios = <2 0>;
     67		output-high;
     68		line-name = "usb-hub-reset";
     69	};
     70};
     71
     72&i2c2 {
     73	pinctrl-names = "default";
     74	pinctrl-0 = <&i2c2_pins_a>;
     75	i2c-scl-rising-time-ns = <185>;
     76	i2c-scl-falling-time-ns = <20>;
     77	status = "okay";
     78	/* spare dmas for other usage */
     79	/delete-property/dmas;
     80	/delete-property/dma-names;
     81	status = "okay";
     82
     83	eeprom@50 {
     84		compatible = "atmel,24c04";
     85		reg = <0x50>;
     86		pagesize = <16>;
     87	};
     88};
     89
     90&i2c4 {
     91	touchscreen@49 {
     92		status = "disabled";
     93	};
     94};
     95
     96&i2c5 {	/* TP7/TP8 */
     97	pinctrl-names = "default";
     98	pinctrl-0 = <&i2c5_pins_a>;
     99	i2c-scl-rising-time-ns = <185>;
    100	i2c-scl-falling-time-ns = <20>;
    101	status = "okay";
    102	/* spare dmas for other usage */
    103	/delete-property/dmas;
    104	/delete-property/dma-names;
    105};
    106
    107&sdmmc3 {
    108	/*
    109	 * On DRC02, the SoM does not have SDIO WiFi. The pins
    110	 * are used for on-board microSD slot instead.
    111	 */
    112	/delete-property/broken-cd;
    113	cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>;
    114	disable-wp;
    115};
    116
    117&spi1 {
    118	pinctrl-names = "default";
    119	pinctrl-0 = <&spi1_pins_a>;
    120	cs-gpios = <&gpioz 3 0>;
    121	/* Use PIO for the display */
    122	/delete-property/dmas;
    123	/delete-property/dma-names;
    124	status = "disabled";	/* Enable once there is display driver */
    125	/*
    126	 * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are
    127	 * also connected to the display board connector.
    128	 */
    129};
    130
    131&usart3 {
    132	pinctrl-names = "default";
    133	pinctrl-0 = <&usart3_pins_a>;
    134	/delete-property/dmas;
    135	/delete-property/dma-names;
    136	status = "okay";
    137};
    138
    139/*
    140 * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1),
    141 *       however the STM32MP1 pinmux cannot map them to UART4 .
    142 */
    143
    144&uart8 {	/* RS485 */
    145	linux,rs485-enabled-at-boot-time;
    146	pinctrl-names = "default";
    147	pinctrl-0 = <&uart8_pins_a>;
    148	rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>;
    149	/delete-property/dmas;
    150	/delete-property/dma-names;
    151	status = "okay";
    152};
    153
    154&usbh_ehci {
    155	phys = <&usbphyc_port0>;
    156	status = "okay";
    157};
    158
    159&usbphyc {
    160	status = "okay";
    161};
    162
    163&usbphyc_port0 {
    164	phy-supply = <&vdd_usb>;
    165};
    166
    167&usbphyc_port1 {
    168	phy-supply = <&vdd_usb>;
    169};