cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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stm32mp15xx-dhcom-picoitx.dtsi (2677B)

      1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
      2/*
      3 * Copyright (C) 2020 Marek Vasut <marex@denx.de>
      4 */
      5
      6#include <dt-bindings/input/input.h>
      7#include <dt-bindings/pwm/pwm.h>
      8
      9/ {
     10	aliases {
     11		serial0 = &uart4;
     12		serial1 = &usart3;
     13		serial2 = &uart8;
     14	};
     15
     16	chosen {
     17		stdout-path = "serial0:115200n8";
     18	};
     19
     20	led {
     21		compatible = "gpio-leds";
     22
     23		led-0 {
     24			label = "yellow:led";
     25			gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>;
     26			default-state = "off";
     27		};
     28	};
     29};
     30
     31&adc {
     32	status = "disabled";
     33};
     34
     35&dac {
     36	status = "disabled";
     37};
     38
     39&fmc {
     40	status = "disabled";
     41};
     42
     43&gpioa {
     44	/*
     45	 * NOTE: The USB Port on the PicoITX needs a PWR_EN signal to enable
     46	 * port power. This signal should be handled by USB power sequencing
     47	 * in order to turn on port power when USB bus is powered up, but so
     48	 * far there is no such functionality.
     49	 */
     50	usb-port-power-hog {
     51		gpio-hog;
     52		gpios = <13 0>;
     53		output-low;
     54		line-name = "usb-port-power";
     55	};
     56};
     57
     58&gpioc {
     59	gpio-line-names = "", "", "", "",
     60			  "", "", "PicoITX-In1", "",
     61			  "", "", "", "",
     62			  "", "", "", "";
     63};
     64
     65&gpiod {
     66	gpio-line-names = "", "", "", "",
     67			  "", "", "DHCOM-B", "",
     68			  "", "", "", "PicoITX-Out1",
     69			  "PicoITX-Out2", "", "", "";
     70};
     71
     72&gpiog {
     73	gpio-line-names = "PicoITX-In2", "", "", "",
     74			  "", "", "", "",
     75			  "DHCOM-L", "", "", "",
     76			  "", "", "", "";
     77};
     78
     79&i2c2 {	/* On board-to-board connector (optional) */
     80	pinctrl-names = "default";
     81	pinctrl-0 = <&i2c2_pins_a>;
     82	i2c-scl-rising-time-ns = <185>;
     83	i2c-scl-falling-time-ns = <20>;
     84	status = "okay";
     85	/* spare dmas for other usage */
     86	/delete-property/dmas;
     87	/delete-property/dma-names;
     88};
     89
     90&i2c5 {	/* On board-to-board connector */
     91	pinctrl-names = "default";
     92	pinctrl-0 = <&i2c5_pins_a>;
     93	i2c-scl-rising-time-ns = <185>;
     94	i2c-scl-falling-time-ns = <20>;
     95	status = "okay";
     96	/* spare dmas for other usage */
     97	/delete-property/dmas;
     98	/delete-property/dma-names;
     99};
    100
    101&ksz8851 {
    102	status = "disabled";
    103};
    104
    105&usart3 {
    106	pinctrl-names = "default";
    107	pinctrl-0 = <&usart3_pins_a>;
    108	/delete-property/dmas;
    109	/delete-property/dma-names;
    110	status = "okay";
    111};
    112
    113&uart8 {
    114	pinctrl-names = "default";
    115	pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>;
    116	/delete-property/dmas;
    117	/delete-property/dma-names;
    118	status = "okay";
    119};
    120
    121&usbh_ehci {
    122	phys = <&usbphyc_port0>;
    123	status = "okay";
    124};
    125
    126&usbh_ohci {
    127	phys = <&usbphyc_port0>;
    128	status = "okay";
    129};
    130
    131&usbotg_hs {
    132	dr_mode = "otg";
    133	pinctrl-0 = <&usbotg_hs_pins_a>;
    134	pinctrl-names = "default";
    135	phy-names = "usb2-phy";
    136	phys = <&usbphyc_port1 0>;
    137	vbus-supply = <&vbus_otg>;
    138	status = "okay";
    139};
    140
    141&usbphyc {
    142	status = "okay";
    143};
    144
    145&usbphyc_port0 {
    146	phy-supply = <&vdd_usb>;
    147};
    148
    149&usbphyc_port1 {
    150	phy-supply = <&vdd_usb>;
    151};