cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sun4i-a10-itead-iteaduino-plus.dts (3245B)


      1/*
      2 * Copyright 2015 Josef Gajdusek <atx@atx.name>
      3 * Copyright 2015 - Marcus Cooper <codekipper@gmail.com>
      4 *
      5 * This file is dual-licensed: you can use it either under the terms
      6 * of the GPL or the X11 license, at your option. Note that this dual
      7 * licensing only applies to this file, and not this project as a
      8 * whole.
      9 *
     10 *  a) This file is free software; you can redistribute it and/or
     11 *     modify it under the terms of the GNU General Public License as
     12 *     published by the Free Software Foundation; either version 2 of the
     13 *     License, or (at your option) any later version.
     14 *
     15 *     This file is distributed in the hope that it will be useful,
     16 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
     17 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     18 *     GNU General Public License for more details.
     19 *
     20 * Or, alternatively,
     21 *
     22 *  b) Permission is hereby granted, free of charge, to any person
     23 *     obtaining a copy of this software and associated documentation
     24 *     files (the "Software"), to deal in the Software without
     25 *     restriction, including without limitation the rights to use,
     26 *     copy, modify, merge, publish, distribute, sublicense, and/or
     27 *     sell copies of the Software, and to permit persons to whom the
     28 *     Software is furnished to do so, subject to the following
     29 *     conditions:
     30 *
     31 *     The above copyright notice and this permission notice shall be
     32 *     included in all copies or substantial portions of the Software.
     33 *
     34 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     35 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
     36 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     37 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
     38 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
     39 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     40 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     41 *     OTHER DEALINGS IN THE SOFTWARE.
     42 */
     43
     44/dts-v1/;
     45#include "sun4i-a10.dtsi"
     46#include "sunxi-itead-core-common.dtsi"
     47
     48/ {
     49	model = "Iteaduino Plus A10";
     50	compatible = "itead,iteaduino-plus-a10", "allwinner,sun4i-a10";
     51};
     52
     53&ahci {
     54	target-supply = <&reg_ahci_5v>;
     55	status = "okay";
     56};
     57
     58&emac {
     59	pinctrl-names = "default";
     60	pinctrl-0 = <&emac_pins>;
     61	phy-handle = <&phy1>;
     62	status = "okay";
     63};
     64
     65&emac_sram {
     66	status = "okay";
     67};
     68
     69&i2c0 {
     70	pinctrl-names = "default";
     71	pinctrl-0 = <&i2c0_pins>;
     72
     73	axp209: pmic@34 {
     74		interrupts = <0>;
     75	};
     76};
     77
     78&i2c1 {
     79	pinctrl-names = "default";
     80	pinctrl-0 = <&i2c1_pins>;
     81	status = "okay";
     82};
     83
     84&i2c2 {
     85	pinctrl-names = "default";
     86	pinctrl-0 = <&i2c2_pins>;
     87	status = "okay";
     88};
     89
     90&ir0 {
     91	pinctrl-names = "default";
     92	pinctrl-0 = <&ir0_rx_pins>;
     93	status = "okay";
     94};
     95
     96&mdio {
     97	status = "okay";
     98
     99	phy1: ethernet-phy@1 {
    100		reg = <1>;
    101	};
    102};
    103
    104&mmc0 {
    105	pinctrl-names = "default";
    106	pinctrl-0 = <&mmc0_pins>;
    107	vmmc-supply = <&reg_vcc3v3>;
    108	bus-width = <4>;
    109	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
    110	status = "okay";
    111};
    112
    113&reg_ahci_5v {
    114	status = "okay";
    115};
    116
    117&spi0 {
    118	pinctrl-names = "default";
    119	pinctrl-0 = <&spi0_pi_pins>,
    120		    <&spi0_cs0_pi_pin>;
    121	status = "okay";
    122};
    123
    124&uart0 {
    125	pinctrl-0 = <&uart0_pb_pins>;
    126};