cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sun7i-a20-haoyu-marsboard.dts (2614B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * Copyright 2021 Conley Lee
      4 * Conley Lee <conleylee@foxmail.com>
      5 */
      6
      7/dts-v1/;
      8#include "sun7i-a20.dtsi"
      9#include "sunxi-common-regulators.dtsi"
     10
     11#include <dt-bindings/gpio/gpio.h>
     12#include <dt-bindings/interrupt-controller/irq.h>
     13
     14/ {
     15	model = "HAOYU Electronics Marsboard A20";
     16	compatible = "haoyu,a20-marsboard", "allwinner,sun7i-a20";
     17
     18	aliases {
     19		serial0 = &uart0;
     20	};
     21
     22	chosen {
     23		stdout-path = "serial0:115200n8";
     24	};
     25
     26	hdmi-connector {
     27		compatible = "hdmi-connector";
     28		type = "a";
     29
     30		port {
     31			hdmi_con_in: endpoint {
     32				remote-endpoint = <&hdmi_out_con>;
     33			};
     34		};
     35	};
     36};
     37
     38&ahci {
     39	target-supply = <&reg_ahci_5v>;
     40	status = "okay";
     41};
     42
     43&codec {
     44	status = "okay";
     45};
     46
     47&cpu0 {
     48	cpu-supply = <&reg_dcdc2>;
     49};
     50
     51&de {
     52	status = "okay";
     53};
     54
     55&ehci0 {
     56	status = "okay";
     57};
     58
     59&ehci1 {
     60	status = "okay";
     61};
     62
     63&gmac {
     64	pinctrl-names = "default";
     65	pinctrl-0 = <&gmac_mii_pins>, <&gmac_txerr>;
     66	phy-handle = <&phy0>;
     67	phy-mode = "mii";
     68	status = "okay";
     69};
     70
     71&hdmi {
     72	status = "okay";
     73};
     74
     75&hdmi_out {
     76	hdmi_out_con: endpoint {
     77		remote-endpoint = <&hdmi_con_in>;
     78	};
     79};
     80
     81&i2c0 {
     82	status = "okay";
     83
     84	axp209: pmic@34 {
     85		reg = <0x34>;
     86		interrupt-parent = <&nmi_intc>;
     87		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
     88	};
     89};
     90
     91&mmc0 {
     92	vmmc-supply = <&reg_vcc3v3>;
     93	bus-width = <4>;
     94	cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
     95	status = "okay";
     96};
     97
     98&gmac_mdio {
     99	phy0: ethernet-phy@0 {
    100		reg = <0>;
    101	};
    102};
    103
    104&ohci0 {
    105	status = "okay";
    106};
    107
    108&ohci1 {
    109	status = "okay";
    110};
    111
    112&otg_sram {
    113	status = "okay";
    114};
    115
    116&pio {
    117	gmac_txerr: gmac-txerr-pin {
    118		pins = "PA17";
    119		function = "gmac";
    120	};
    121};
    122
    123&reg_ahci_5v {
    124	status = "okay";
    125};
    126
    127#include "axp209.dtsi"
    128
    129&ac_power_supply {
    130	status = "okay";
    131};
    132
    133&reg_dcdc2 {
    134	regulator-always-on;
    135	regulator-min-microvolt = <1000000>;
    136	regulator-max-microvolt = <1450000>;
    137	regulator-name = "vdd-cpu";
    138};
    139
    140&reg_dcdc3 {
    141	regulator-always-on;
    142	regulator-min-microvolt = <1000000>;
    143	regulator-max-microvolt = <1400000>;
    144	regulator-name = "vdd-int-dll";
    145};
    146
    147&reg_ldo1 {
    148	regulator-name = "vdd-rtc";
    149};
    150
    151&reg_ldo2 {
    152	regulator-always-on;
    153	regulator-min-microvolt = <3000000>;
    154	regulator-max-microvolt = <3000000>;
    155	regulator-name = "avcc";
    156};
    157
    158&reg_usb1_vbus {
    159	status = "okay";
    160};
    161
    162&reg_usb2_vbus {
    163	status = "okay";
    164};
    165
    166&uart0 {
    167	pinctrl-names = "default";
    168	pinctrl-0 = <&uart0_pb_pins>;
    169	status = "okay";
    170};
    171
    172&usb_otg {
    173	dr_mode = "otg";
    174	status = "okay";
    175};
    176
    177&usbphy {
    178	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
    179	usb1_vbus-supply = <&reg_usb1_vbus>;
    180	usb2_vbus-supply = <&reg_usb2_vbus>;
    181	status = "okay";
    182};