sun8i-r40.dtsi (32825B)
1/* 2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org> 3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io> 4 * 5 * This file is dual-licensed: you can use it either under the terms 6 * of the GPL or the X11 license, at your option. Note that this dual 7 * licensing only applies to this file, and not this project as a 8 * whole. 9 * 10 * a) This file is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of the 13 * License, or (at your option) any later version. 14 * 15 * This file is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * Or, alternatively, 21 * 22 * b) Permission is hereby granted, free of charge, to any person 23 * obtaining a copy of this software and associated documentation 24 * files (the "Software"), to deal in the Software without 25 * restriction, including without limitation the rights to use, 26 * copy, modify, merge, publish, distribute, sublicense, and/or 27 * sell copies of the Software, and to permit persons to whom the 28 * Software is furnished to do so, subject to the following 29 * conditions: 30 * 31 * The above copyright notice and this permission notice shall be 32 * included in all copies or substantial portions of the Software. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 * OTHER DEALINGS IN THE SOFTWARE. 42 */ 43 44#include <dt-bindings/interrupt-controller/arm-gic.h> 45#include <dt-bindings/clock/sun8i-de2.h> 46#include <dt-bindings/clock/sun8i-r40-ccu.h> 47#include <dt-bindings/clock/sun8i-tcon-top.h> 48#include <dt-bindings/reset/sun8i-r40-ccu.h> 49#include <dt-bindings/reset/sun8i-de2.h> 50#include <dt-bindings/thermal/thermal.h> 51 52/ { 53 #address-cells = <1>; 54 #size-cells = <1>; 55 interrupt-parent = <&gic>; 56 57 clocks { 58 #address-cells = <1>; 59 #size-cells = <1>; 60 ranges; 61 62 osc24M: osc24M { 63 #clock-cells = <0>; 64 compatible = "fixed-clock"; 65 clock-frequency = <24000000>; 66 clock-accuracy = <50000>; 67 clock-output-names = "osc24M"; 68 }; 69 70 osc32k: osc32k { 71 #clock-cells = <0>; 72 compatible = "fixed-clock"; 73 clock-frequency = <32768>; 74 clock-accuracy = <20000>; 75 clock-output-names = "ext-osc32k"; 76 }; 77 }; 78 79 cpus { 80 #address-cells = <1>; 81 #size-cells = <0>; 82 83 cpu0: cpu@0 { 84 compatible = "arm,cortex-a7"; 85 device_type = "cpu"; 86 reg = <0>; 87 }; 88 89 cpu1: cpu@1 { 90 compatible = "arm,cortex-a7"; 91 device_type = "cpu"; 92 reg = <1>; 93 }; 94 95 cpu2: cpu@2 { 96 compatible = "arm,cortex-a7"; 97 device_type = "cpu"; 98 reg = <2>; 99 }; 100 101 cpu3: cpu@3 { 102 compatible = "arm,cortex-a7"; 103 device_type = "cpu"; 104 reg = <3>; 105 }; 106 }; 107 108 de: display-engine { 109 compatible = "allwinner,sun8i-r40-display-engine"; 110 allwinner,pipelines = <&mixer0>, <&mixer1>; 111 status = "disabled"; 112 }; 113 114 thermal-zones { 115 cpu_thermal: cpu0-thermal { 116 /* milliseconds */ 117 polling-delay-passive = <0>; 118 polling-delay = <0>; 119 thermal-sensors = <&ths 0>; 120 }; 121 122 gpu_thermal: gpu-thermal { 123 /* milliseconds */ 124 polling-delay-passive = <0>; 125 polling-delay = <0>; 126 thermal-sensors = <&ths 1>; 127 }; 128 }; 129 130 soc { 131 compatible = "simple-bus"; 132 #address-cells = <1>; 133 #size-cells = <1>; 134 ranges; 135 136 display_clocks: clock@1000000 { 137 compatible = "allwinner,sun8i-r40-de2-clk", 138 "allwinner,sun8i-h3-de2-clk"; 139 reg = <0x01000000 0x10000>; 140 clocks = <&ccu CLK_BUS_DE>, 141 <&ccu CLK_DE>; 142 clock-names = "bus", 143 "mod"; 144 resets = <&ccu RST_BUS_DE>; 145 #clock-cells = <1>; 146 #reset-cells = <1>; 147 }; 148 149 mixer0: mixer@1100000 { 150 compatible = "allwinner,sun8i-r40-de2-mixer-0"; 151 reg = <0x01100000 0x100000>; 152 clocks = <&display_clocks CLK_BUS_MIXER0>, 153 <&display_clocks CLK_MIXER0>; 154 clock-names = "bus", 155 "mod"; 156 resets = <&display_clocks RST_MIXER0>; 157 158 ports { 159 #address-cells = <1>; 160 #size-cells = <0>; 161 162 mixer0_out: port@1 { 163 reg = <1>; 164 mixer0_out_tcon_top: endpoint { 165 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 166 }; 167 }; 168 }; 169 }; 170 171 mixer1: mixer@1200000 { 172 compatible = "allwinner,sun8i-r40-de2-mixer-1"; 173 reg = <0x01200000 0x100000>; 174 clocks = <&display_clocks CLK_BUS_MIXER1>, 175 <&display_clocks CLK_MIXER1>; 176 clock-names = "bus", 177 "mod"; 178 resets = <&display_clocks RST_WB>; 179 180 ports { 181 #address-cells = <1>; 182 #size-cells = <0>; 183 184 mixer1_out: port@1 { 185 reg = <1>; 186 mixer1_out_tcon_top: endpoint { 187 remote-endpoint = <&tcon_top_mixer1_in_mixer1>; 188 }; 189 }; 190 }; 191 }; 192 193 deinterlace: deinterlace@1400000 { 194 compatible = "allwinner,sun8i-r40-deinterlace", 195 "allwinner,sun8i-h3-deinterlace"; 196 reg = <0x01400000 0x20000>; 197 clocks = <&ccu CLK_BUS_DEINTERLACE>, 198 <&ccu CLK_DEINTERLACE>, 199 /* 200 * NOTE: Contrary to what datasheet claims, 201 * DRAM deinterlace gate doesn't exist and 202 * it's shared with CSI1. 203 */ 204 <&ccu CLK_DRAM_CSI1>; 205 clock-names = "bus", "mod", "ram"; 206 resets = <&ccu RST_BUS_DEINTERLACE>; 207 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 208 interconnects = <&mbus 9>; 209 interconnect-names = "dma-mem"; 210 }; 211 212 syscon: system-control@1c00000 { 213 compatible = "allwinner,sun8i-r40-system-control", 214 "allwinner,sun4i-a10-system-control"; 215 reg = <0x01c00000 0x30>; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 ranges; 219 220 sram_c: sram@1d00000 { 221 compatible = "mmio-sram"; 222 reg = <0x01d00000 0xd0000>; 223 #address-cells = <1>; 224 #size-cells = <1>; 225 ranges = <0 0x01d00000 0xd0000>; 226 227 ve_sram: sram-section@0 { 228 compatible = "allwinner,sun8i-r40-sram-c1", 229 "allwinner,sun4i-a10-sram-c1"; 230 reg = <0x000000 0x80000>; 231 }; 232 }; 233 }; 234 235 nmi_intc: interrupt-controller@1c00030 { 236 compatible = "allwinner,sun7i-a20-sc-nmi"; 237 interrupt-controller; 238 #interrupt-cells = <2>; 239 reg = <0x01c00030 0x0c>; 240 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 241 }; 242 243 dma: dma-controller@1c02000 { 244 compatible = "allwinner,sun8i-r40-dma", 245 "allwinner,sun50i-a64-dma"; 246 reg = <0x01c02000 0x1000>; 247 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&ccu CLK_BUS_DMA>; 249 dma-channels = <16>; 250 dma-requests = <31>; 251 resets = <&ccu RST_BUS_DMA>; 252 #dma-cells = <1>; 253 }; 254 255 spi0: spi@1c05000 { 256 compatible = "allwinner,sun8i-r40-spi", 257 "allwinner,sun8i-h3-spi"; 258 reg = <0x01c05000 0x1000>; 259 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 261 clock-names = "ahb", "mod"; 262 resets = <&ccu RST_BUS_SPI0>; 263 status = "disabled"; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 }; 267 268 spi1: spi@1c06000 { 269 compatible = "allwinner,sun8i-r40-spi", 270 "allwinner,sun8i-h3-spi"; 271 reg = <0x01c06000 0x1000>; 272 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 274 clock-names = "ahb", "mod"; 275 resets = <&ccu RST_BUS_SPI1>; 276 status = "disabled"; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 }; 280 281 csi0: csi@1c09000 { 282 compatible = "allwinner,sun8i-r40-csi0", 283 "allwinner,sun7i-a20-csi0"; 284 reg = <0x01c09000 0x1000>; 285 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>, 287 <&ccu CLK_DRAM_CSI0>; 288 clock-names = "bus", "isp", "ram"; 289 resets = <&ccu RST_BUS_CSI0>; 290 interconnects = <&mbus 5>; 291 interconnect-names = "dma-mem"; 292 status = "disabled"; 293 }; 294 295 video-codec@1c0e000 { 296 compatible = "allwinner,sun8i-r40-video-engine"; 297 reg = <0x01c0e000 0x1000>; 298 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 299 <&ccu CLK_DRAM_VE>; 300 clock-names = "ahb", "mod", "ram"; 301 resets = <&ccu RST_BUS_VE>; 302 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 303 allwinner,sram = <&ve_sram 1>; 304 }; 305 306 mmc0: mmc@1c0f000 { 307 compatible = "allwinner,sun8i-r40-mmc", 308 "allwinner,sun50i-a64-mmc"; 309 reg = <0x01c0f000 0x1000>; 310 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 311 clock-names = "ahb", "mmc"; 312 resets = <&ccu RST_BUS_MMC0>; 313 reset-names = "ahb"; 314 pinctrl-0 = <&mmc0_pins>; 315 pinctrl-names = "default"; 316 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 317 status = "disabled"; 318 #address-cells = <1>; 319 #size-cells = <0>; 320 }; 321 322 mmc1: mmc@1c10000 { 323 compatible = "allwinner,sun8i-r40-mmc", 324 "allwinner,sun50i-a64-mmc"; 325 reg = <0x01c10000 0x1000>; 326 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 327 clock-names = "ahb", "mmc"; 328 resets = <&ccu RST_BUS_MMC1>; 329 reset-names = "ahb"; 330 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 331 status = "disabled"; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 }; 335 336 mmc2: mmc@1c11000 { 337 compatible = "allwinner,sun8i-r40-emmc", 338 "allwinner,sun50i-a64-emmc"; 339 reg = <0x01c11000 0x1000>; 340 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 341 clock-names = "ahb", "mmc"; 342 resets = <&ccu RST_BUS_MMC2>; 343 reset-names = "ahb"; 344 pinctrl-0 = <&mmc2_pins>; 345 pinctrl-names = "default"; 346 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 347 status = "disabled"; 348 #address-cells = <1>; 349 #size-cells = <0>; 350 }; 351 352 mmc3: mmc@1c12000 { 353 compatible = "allwinner,sun8i-r40-mmc", 354 "allwinner,sun50i-a64-mmc"; 355 reg = <0x01c12000 0x1000>; 356 clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>; 357 clock-names = "ahb", "mmc"; 358 resets = <&ccu RST_BUS_MMC3>; 359 reset-names = "ahb"; 360 pinctrl-0 = <&mmc3_pins>; 361 pinctrl-names = "default"; 362 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 363 status = "disabled"; 364 #address-cells = <1>; 365 #size-cells = <0>; 366 }; 367 368 usbphy: phy@1c13400 { 369 compatible = "allwinner,sun8i-r40-usb-phy"; 370 reg = <0x01c13400 0x14>, 371 <0x01c14800 0x4>, 372 <0x01c19800 0x4>, 373 <0x01c1c800 0x4>; 374 reg-names = "phy_ctrl", 375 "pmu0", 376 "pmu1", 377 "pmu2"; 378 clocks = <&ccu CLK_USB_PHY0>, 379 <&ccu CLK_USB_PHY1>, 380 <&ccu CLK_USB_PHY2>; 381 clock-names = "usb0_phy", 382 "usb1_phy", 383 "usb2_phy"; 384 resets = <&ccu RST_USB_PHY0>, 385 <&ccu RST_USB_PHY1>, 386 <&ccu RST_USB_PHY2>; 387 reset-names = "usb0_reset", 388 "usb1_reset", 389 "usb2_reset"; 390 status = "disabled"; 391 #phy-cells = <1>; 392 }; 393 394 crypto: crypto@1c15000 { 395 compatible = "allwinner,sun8i-r40-crypto"; 396 reg = <0x01c15000 0x1000>; 397 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 399 clock-names = "bus", "mod"; 400 resets = <&ccu RST_BUS_CE>; 401 }; 402 403 spi2: spi@1c17000 { 404 compatible = "allwinner,sun8i-r40-spi", 405 "allwinner,sun8i-h3-spi"; 406 reg = <0x01c17000 0x1000>; 407 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; 409 clock-names = "ahb", "mod"; 410 resets = <&ccu RST_BUS_SPI2>; 411 status = "disabled"; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 }; 415 416 ahci: sata@1c18000 { 417 compatible = "allwinner,sun8i-r40-ahci"; 418 reg = <0x01c18000 0x1000>; 419 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; 421 resets = <&ccu RST_BUS_SATA>; 422 reset-names = "ahci"; 423 status = "disabled"; 424 }; 425 426 ehci1: usb@1c19000 { 427 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; 428 reg = <0x01c19000 0x100>; 429 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&ccu CLK_BUS_EHCI1>; 431 resets = <&ccu RST_BUS_EHCI1>; 432 phys = <&usbphy 1>; 433 phy-names = "usb"; 434 status = "disabled"; 435 }; 436 437 ohci1: usb@1c19400 { 438 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; 439 reg = <0x01c19400 0x100>; 440 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&ccu CLK_BUS_OHCI1>, 442 <&ccu CLK_USB_OHCI1>; 443 resets = <&ccu RST_BUS_OHCI1>; 444 phys = <&usbphy 1>; 445 phy-names = "usb"; 446 status = "disabled"; 447 }; 448 449 ehci2: usb@1c1c000 { 450 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; 451 reg = <0x01c1c000 0x100>; 452 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&ccu CLK_BUS_EHCI2>; 454 resets = <&ccu RST_BUS_EHCI2>; 455 phys = <&usbphy 2>; 456 phy-names = "usb"; 457 status = "disabled"; 458 }; 459 460 ohci2: usb@1c1c400 { 461 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; 462 reg = <0x01c1c400 0x100>; 463 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&ccu CLK_BUS_OHCI2>, 465 <&ccu CLK_USB_OHCI2>; 466 resets = <&ccu RST_BUS_OHCI2>; 467 phys = <&usbphy 2>; 468 phy-names = "usb"; 469 status = "disabled"; 470 }; 471 472 spi3: spi@1c1f000 { 473 compatible = "allwinner,sun8i-r40-spi", 474 "allwinner,sun8i-h3-spi"; 475 reg = <0x01c1f000 0x1000>; 476 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>; 478 clock-names = "ahb", "mod"; 479 resets = <&ccu RST_BUS_SPI3>; 480 status = "disabled"; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 }; 484 485 ccu: clock@1c20000 { 486 compatible = "allwinner,sun8i-r40-ccu"; 487 reg = <0x01c20000 0x400>; 488 clocks = <&osc24M>, <&rtc 0>; 489 clock-names = "hosc", "losc"; 490 #clock-cells = <1>; 491 #reset-cells = <1>; 492 }; 493 494 rtc: rtc@1c20400 { 495 compatible = "allwinner,sun8i-r40-rtc"; 496 reg = <0x01c20400 0x400>; 497 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 498 clock-output-names = "osc32k", "osc32k-out"; 499 clocks = <&osc32k>; 500 #clock-cells = <1>; 501 }; 502 503 pio: pinctrl@1c20800 { 504 compatible = "allwinner,sun8i-r40-pinctrl"; 505 reg = <0x01c20800 0x400>; 506 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 508 clock-names = "apb", "hosc", "losc"; 509 gpio-controller; 510 interrupt-controller; 511 #interrupt-cells = <3>; 512 #gpio-cells = <3>; 513 514 can_ph_pins: can-ph-pins { 515 pins = "PH20", "PH21"; 516 function = "can"; 517 }; 518 519 can_pa_pins: can-pa-pins { 520 pins = "PA16", "PA17"; 521 function = "can"; 522 }; 523 524 clk_out_a_pin: clk-out-a-pin { 525 pins = "PI12"; 526 function = "clk_out_a"; 527 }; 528 529 /omit-if-no-ref/ 530 csi0_8bits_pins: csi0-8bits-pins { 531 pins = "PE0", "PE2", "PE3", "PE4", "PE5", 532 "PE6", "PE7", "PE8", "PE9", "PE10", 533 "PE11"; 534 function = "csi0"; 535 }; 536 537 /omit-if-no-ref/ 538 csi0_mclk_pin: csi0-mclk-pin { 539 pins = "PE1"; 540 function = "csi0"; 541 }; 542 543 gmac_rgmii_pins: gmac-rgmii-pins { 544 pins = "PA0", "PA1", "PA2", "PA3", 545 "PA4", "PA5", "PA6", "PA7", 546 "PA8", "PA10", "PA11", "PA12", 547 "PA13", "PA15", "PA16"; 548 function = "gmac"; 549 /* 550 * data lines in RGMII mode use DDR mode 551 * and need a higher signal drive strength 552 */ 553 drive-strength = <40>; 554 }; 555 556 i2c0_pins: i2c0-pins { 557 pins = "PB0", "PB1"; 558 function = "i2c0"; 559 }; 560 561 i2c1_pins: i2c1-pins { 562 pins = "PB18", "PB19"; 563 function = "i2c1"; 564 }; 565 566 i2c2_pins: i2c2-pins { 567 pins = "PB20", "PB21"; 568 function = "i2c2"; 569 }; 570 571 i2c3_pins: i2c3-pins { 572 pins = "PI0", "PI1"; 573 function = "i2c3"; 574 }; 575 576 i2c4_pins: i2c4-pins { 577 pins = "PI2", "PI3"; 578 function = "i2c4"; 579 }; 580 581 ir0_pins: ir0-pins { 582 pins = "PB4"; 583 function = "ir0"; 584 }; 585 586 ir1_pins: ir1-pins { 587 pins = "PB23"; 588 function = "ir1"; 589 }; 590 591 mmc0_pins: mmc0-pins { 592 pins = "PF0", "PF1", "PF2", 593 "PF3", "PF4", "PF5"; 594 function = "mmc0"; 595 drive-strength = <30>; 596 bias-pull-up; 597 }; 598 599 mmc1_pg_pins: mmc1-pg-pins { 600 pins = "PG0", "PG1", "PG2", 601 "PG3", "PG4", "PG5"; 602 function = "mmc1"; 603 drive-strength = <30>; 604 bias-pull-up; 605 }; 606 607 mmc2_pins: mmc2-pins { 608 pins = "PC5", "PC6", "PC7", "PC8", "PC9", 609 "PC10", "PC11", "PC12", "PC13", "PC14", 610 "PC15", "PC24"; 611 function = "mmc2"; 612 drive-strength = <30>; 613 bias-pull-up; 614 }; 615 616 /omit-if-no-ref/ 617 mmc3_pins: mmc3-pins { 618 pins = "PI4", "PI5", "PI6", 619 "PI7", "PI8", "PI9"; 620 function = "mmc3"; 621 drive-strength = <30>; 622 bias-pull-up; 623 }; 624 625 /omit-if-no-ref/ 626 spi0_pc_pins: spi0-pc-pins { 627 pins = "PC0", "PC1", "PC2"; 628 function = "spi0"; 629 }; 630 631 /omit-if-no-ref/ 632 spi0_cs0_pc_pin: spi0-cs0-pc-pin { 633 pins = "PC23"; 634 function = "spi0"; 635 }; 636 637 /omit-if-no-ref/ 638 spi1_pi_pins: spi1-pi-pins { 639 pins = "PI17", "PI18", "PI19"; 640 function = "spi1"; 641 }; 642 643 /omit-if-no-ref/ 644 spi1_cs0_pi_pin: spi1-cs0-pi-pin { 645 pins = "PI16"; 646 function = "spi1"; 647 }; 648 649 /omit-if-no-ref/ 650 spi1_cs1_pi_pin: spi1-cs1-pi-pin { 651 pins = "PI15"; 652 function = "spi1"; 653 }; 654 655 /omit-if-no-ref/ 656 uart0_pb_pins: uart0-pb-pins { 657 pins = "PB22", "PB23"; 658 function = "uart0"; 659 }; 660 661 /omit-if-no-ref/ 662 uart2_pi_pins: uart2-pi-pins { 663 pins = "PI18", "PI19"; 664 function = "uart2"; 665 }; 666 667 /omit-if-no-ref/ 668 uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{ 669 pins = "PI16", "PI17"; 670 function = "uart2"; 671 }; 672 673 /omit-if-no-ref/ 674 uart3_pg_pins: uart3-pg-pins { 675 pins = "PG6", "PG7"; 676 function = "uart3"; 677 }; 678 679 /omit-if-no-ref/ 680 uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins { 681 pins = "PG8", "PG9"; 682 function = "uart3"; 683 }; 684 685 /omit-if-no-ref/ 686 uart4_pg_pins: uart4-pg-pins { 687 pins = "PG10", "PG11"; 688 function = "uart4"; 689 }; 690 691 /omit-if-no-ref/ 692 uart5_ph_pins: uart5-ph-pins { 693 pins = "PH6", "PH7"; 694 function = "uart5"; 695 }; 696 697 /omit-if-no-ref/ 698 uart7_pi_pins: uart7-pi-pins { 699 pins = "PI20", "PI21"; 700 function = "uart7"; 701 }; 702 }; 703 704 timer@1c20c00 { 705 compatible = "allwinner,sun4i-a10-timer"; 706 reg = <0x01c20c00 0x90>; 707 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&osc24M>; 714 }; 715 716 wdt: watchdog@1c20c90 { 717 compatible = "allwinner,sun4i-a10-wdt"; 718 reg = <0x01c20c90 0x10>; 719 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&osc24M>; 721 }; 722 723 ir0: ir@1c21800 { 724 compatible = "allwinner,sun8i-r40-ir", 725 "allwinner,sun6i-a31-ir"; 726 reg = <0x01c21800 0x400>; 727 pinctrl-0 = <&ir0_pins>; 728 pinctrl-names = "default"; 729 clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>; 730 clock-names = "apb", "ir"; 731 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 732 resets = <&ccu RST_BUS_IR0>; 733 status = "disabled"; 734 }; 735 736 ir1: ir@1c21c00 { 737 compatible = "allwinner,sun8i-r40-ir", 738 "allwinner,sun6i-a31-ir"; 739 reg = <0x01c21c00 0x400>; 740 pinctrl-0 = <&ir1_pins>; 741 pinctrl-names = "default"; 742 clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>; 743 clock-names = "apb", "ir"; 744 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 745 resets = <&ccu RST_BUS_IR1>; 746 status = "disabled"; 747 }; 748 749 i2s0: i2s@1c22000 { 750 #sound-dai-cells = <0>; 751 compatible = "allwinner,sun8i-r40-i2s", 752 "allwinner,sun8i-h3-i2s"; 753 reg = <0x01c22000 0x400>; 754 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 756 clock-names = "apb", "mod"; 757 resets = <&ccu RST_BUS_I2S0>; 758 dmas = <&dma 3>, <&dma 3>; 759 dma-names = "rx", "tx"; 760 }; 761 762 i2s1: i2s@1c22400 { 763 #sound-dai-cells = <0>; 764 compatible = "allwinner,sun8i-r40-i2s", 765 "allwinner,sun8i-h3-i2s"; 766 reg = <0x01c22400 0x400>; 767 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 768 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 769 clock-names = "apb", "mod"; 770 resets = <&ccu RST_BUS_I2S1>; 771 dmas = <&dma 4>, <&dma 4>; 772 dma-names = "rx", "tx"; 773 }; 774 775 i2s2: i2s@1c22800 { 776 #sound-dai-cells = <0>; 777 compatible = "allwinner,sun8i-r40-i2s", 778 "allwinner,sun8i-h3-i2s"; 779 reg = <0x01c22800 0x400>; 780 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; 782 clock-names = "apb", "mod"; 783 resets = <&ccu RST_BUS_I2S2>; 784 dmas = <&dma 6>, <&dma 6>; 785 dma-names = "rx", "tx"; 786 }; 787 788 ths: thermal-sensor@1c24c00 { 789 compatible = "allwinner,sun8i-r40-ths"; 790 reg = <0x01c24c00 0x100>; 791 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 792 clock-names = "bus", "mod"; 793 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 794 resets = <&ccu RST_BUS_THS>; 795 /* TODO: add nvmem-cells for calibration */ 796 #thermal-sensor-cells = <1>; 797 }; 798 799 uart0: serial@1c28000 { 800 compatible = "snps,dw-apb-uart"; 801 reg = <0x01c28000 0x400>; 802 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 803 reg-shift = <2>; 804 reg-io-width = <4>; 805 clocks = <&ccu CLK_BUS_UART0>; 806 resets = <&ccu RST_BUS_UART0>; 807 status = "disabled"; 808 }; 809 810 uart1: serial@1c28400 { 811 compatible = "snps,dw-apb-uart"; 812 reg = <0x01c28400 0x400>; 813 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 814 reg-shift = <2>; 815 reg-io-width = <4>; 816 clocks = <&ccu CLK_BUS_UART1>; 817 resets = <&ccu RST_BUS_UART1>; 818 status = "disabled"; 819 }; 820 821 uart2: serial@1c28800 { 822 compatible = "snps,dw-apb-uart"; 823 reg = <0x01c28800 0x400>; 824 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 825 reg-shift = <2>; 826 reg-io-width = <4>; 827 clocks = <&ccu CLK_BUS_UART2>; 828 resets = <&ccu RST_BUS_UART2>; 829 status = "disabled"; 830 }; 831 832 uart3: serial@1c28c00 { 833 compatible = "snps,dw-apb-uart"; 834 reg = <0x01c28c00 0x400>; 835 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 836 reg-shift = <2>; 837 reg-io-width = <4>; 838 clocks = <&ccu CLK_BUS_UART3>; 839 resets = <&ccu RST_BUS_UART3>; 840 status = "disabled"; 841 }; 842 843 uart4: serial@1c29000 { 844 compatible = "snps,dw-apb-uart"; 845 reg = <0x01c29000 0x400>; 846 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 847 reg-shift = <2>; 848 reg-io-width = <4>; 849 clocks = <&ccu CLK_BUS_UART4>; 850 resets = <&ccu RST_BUS_UART4>; 851 status = "disabled"; 852 }; 853 854 uart5: serial@1c29400 { 855 compatible = "snps,dw-apb-uart"; 856 reg = <0x01c29400 0x400>; 857 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 858 reg-shift = <2>; 859 reg-io-width = <4>; 860 clocks = <&ccu CLK_BUS_UART5>; 861 resets = <&ccu RST_BUS_UART5>; 862 status = "disabled"; 863 }; 864 865 uart6: serial@1c29800 { 866 compatible = "snps,dw-apb-uart"; 867 reg = <0x01c29800 0x400>; 868 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 869 reg-shift = <2>; 870 reg-io-width = <4>; 871 clocks = <&ccu CLK_BUS_UART6>; 872 resets = <&ccu RST_BUS_UART6>; 873 status = "disabled"; 874 }; 875 876 uart7: serial@1c29c00 { 877 compatible = "snps,dw-apb-uart"; 878 reg = <0x01c29c00 0x400>; 879 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 880 reg-shift = <2>; 881 reg-io-width = <4>; 882 clocks = <&ccu CLK_BUS_UART7>; 883 resets = <&ccu RST_BUS_UART7>; 884 status = "disabled"; 885 }; 886 887 i2c0: i2c@1c2ac00 { 888 compatible = "allwinner,sun6i-a31-i2c"; 889 reg = <0x01c2ac00 0x400>; 890 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&ccu CLK_BUS_I2C0>; 892 resets = <&ccu RST_BUS_I2C0>; 893 pinctrl-0 = <&i2c0_pins>; 894 pinctrl-names = "default"; 895 status = "disabled"; 896 #address-cells = <1>; 897 #size-cells = <0>; 898 }; 899 900 i2c1: i2c@1c2b000 { 901 compatible = "allwinner,sun6i-a31-i2c"; 902 reg = <0x01c2b000 0x400>; 903 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&ccu CLK_BUS_I2C1>; 905 resets = <&ccu RST_BUS_I2C1>; 906 pinctrl-0 = <&i2c1_pins>; 907 pinctrl-names = "default"; 908 status = "disabled"; 909 #address-cells = <1>; 910 #size-cells = <0>; 911 }; 912 913 i2c2: i2c@1c2b400 { 914 compatible = "allwinner,sun6i-a31-i2c"; 915 reg = <0x01c2b400 0x400>; 916 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 917 clocks = <&ccu CLK_BUS_I2C2>; 918 resets = <&ccu RST_BUS_I2C2>; 919 pinctrl-0 = <&i2c2_pins>; 920 pinctrl-names = "default"; 921 status = "disabled"; 922 #address-cells = <1>; 923 #size-cells = <0>; 924 }; 925 926 i2c3: i2c@1c2b800 { 927 compatible = "allwinner,sun6i-a31-i2c"; 928 reg = <0x01c2b800 0x400>; 929 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&ccu CLK_BUS_I2C3>; 931 resets = <&ccu RST_BUS_I2C3>; 932 pinctrl-0 = <&i2c3_pins>; 933 pinctrl-names = "default"; 934 status = "disabled"; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 }; 938 939 can0: can@1c2bc00 { 940 compatible = "allwinner,sun8i-r40-can"; 941 reg = <0x01c2bc00 0x400>; 942 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 943 clocks = <&ccu CLK_BUS_CAN>; 944 resets = <&ccu RST_BUS_CAN>; 945 status = "disabled"; 946 }; 947 948 i2c4: i2c@1c2c000 { 949 compatible = "allwinner,sun6i-a31-i2c"; 950 reg = <0x01c2c000 0x400>; 951 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 952 clocks = <&ccu CLK_BUS_I2C4>; 953 resets = <&ccu RST_BUS_I2C4>; 954 pinctrl-0 = <&i2c4_pins>; 955 pinctrl-names = "default"; 956 status = "disabled"; 957 #address-cells = <1>; 958 #size-cells = <0>; 959 }; 960 961 mali: gpu@1c40000 { 962 compatible = "allwinner,sun8i-r40-mali", "arm,mali-400"; 963 reg = <0x01c40000 0x10000>; 964 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 971 interrupt-names = "gp", 972 "gpmmu", 973 "pp0", 974 "ppmmu0", 975 "pp1", 976 "ppmmu1", 977 "pmu"; 978 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 979 clock-names = "bus", "core"; 980 resets = <&ccu RST_BUS_GPU>; 981 }; 982 983 gmac: ethernet@1c50000 { 984 compatible = "allwinner,sun8i-r40-gmac"; 985 syscon = <&ccu>; 986 reg = <0x01c50000 0x10000>; 987 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 988 interrupt-names = "macirq"; 989 resets = <&ccu RST_BUS_GMAC>; 990 reset-names = "stmmaceth"; 991 clocks = <&ccu CLK_BUS_GMAC>; 992 clock-names = "stmmaceth"; 993 status = "disabled"; 994 995 gmac_mdio: mdio { 996 compatible = "snps,dwmac-mdio"; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 }; 1000 }; 1001 1002 mbus: dram-controller@1c62000 { 1003 compatible = "allwinner,sun8i-r40-mbus"; 1004 reg = <0x01c62000 0x1000>; 1005 clocks = <&ccu 155>; 1006 #address-cells = <1>; 1007 #size-cells = <1>; 1008 dma-ranges = <0x00000000 0x40000000 0x80000000>; 1009 #interconnect-cells = <1>; 1010 }; 1011 1012 tcon_top: tcon-top@1c70000 { 1013 compatible = "allwinner,sun8i-r40-tcon-top"; 1014 reg = <0x01c70000 0x1000>; 1015 clocks = <&ccu CLK_BUS_TCON_TOP>, 1016 <&ccu CLK_TCON_TV0>, 1017 <&ccu CLK_TVE0>, 1018 <&ccu CLK_TCON_TV1>, 1019 <&ccu CLK_TVE1>, 1020 <&ccu CLK_DSI_DPHY>; 1021 clock-names = "bus", 1022 "tcon-tv0", 1023 "tve0", 1024 "tcon-tv1", 1025 "tve1", 1026 "dsi"; 1027 clock-output-names = "tcon-top-tv0", 1028 "tcon-top-tv1", 1029 "tcon-top-dsi"; 1030 resets = <&ccu RST_BUS_TCON_TOP>; 1031 #clock-cells = <1>; 1032 1033 ports { 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 1037 tcon_top_mixer0_in: port@0 { 1038 reg = <0>; 1039 1040 tcon_top_mixer0_in_mixer0: endpoint { 1041 remote-endpoint = <&mixer0_out_tcon_top>; 1042 }; 1043 }; 1044 1045 tcon_top_mixer0_out: port@1 { 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 reg = <1>; 1049 1050 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { 1051 reg = <0>; 1052 }; 1053 1054 tcon_top_mixer0_out_tcon_lcd1: endpoint@1 { 1055 reg = <1>; 1056 }; 1057 1058 tcon_top_mixer0_out_tcon_tv0: endpoint@2 { 1059 reg = <2>; 1060 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; 1061 }; 1062 1063 tcon_top_mixer0_out_tcon_tv1: endpoint@3 { 1064 reg = <3>; 1065 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>; 1066 }; 1067 }; 1068 1069 tcon_top_mixer1_in: port@2 { 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 reg = <2>; 1073 1074 tcon_top_mixer1_in_mixer1: endpoint@1 { 1075 reg = <1>; 1076 remote-endpoint = <&mixer1_out_tcon_top>; 1077 }; 1078 }; 1079 1080 tcon_top_mixer1_out: port@3 { 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 reg = <3>; 1084 1085 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { 1086 reg = <0>; 1087 }; 1088 1089 tcon_top_mixer1_out_tcon_lcd1: endpoint@1 { 1090 reg = <1>; 1091 }; 1092 1093 tcon_top_mixer1_out_tcon_tv0: endpoint@2 { 1094 reg = <2>; 1095 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; 1096 }; 1097 1098 tcon_top_mixer1_out_tcon_tv1: endpoint@3 { 1099 reg = <3>; 1100 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>; 1101 }; 1102 }; 1103 1104 tcon_top_hdmi_in: port@4 { 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 reg = <4>; 1108 1109 tcon_top_hdmi_in_tcon_tv0: endpoint@0 { 1110 reg = <0>; 1111 remote-endpoint = <&tcon_tv0_out_tcon_top>; 1112 }; 1113 1114 tcon_top_hdmi_in_tcon_tv1: endpoint@1 { 1115 reg = <1>; 1116 remote-endpoint = <&tcon_tv1_out_tcon_top>; 1117 }; 1118 }; 1119 1120 tcon_top_hdmi_out: port@5 { 1121 reg = <5>; 1122 1123 tcon_top_hdmi_out_hdmi: endpoint { 1124 remote-endpoint = <&hdmi_in_tcon_top>; 1125 }; 1126 }; 1127 }; 1128 }; 1129 1130 tcon_tv0: lcd-controller@1c73000 { 1131 compatible = "allwinner,sun8i-r40-tcon-tv"; 1132 reg = <0x01c73000 0x1000>; 1133 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1134 clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>; 1135 clock-names = "ahb", "tcon-ch1"; 1136 resets = <&ccu RST_BUS_TCON_TV0>; 1137 reset-names = "lcd"; 1138 status = "disabled"; 1139 1140 ports { 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 1144 tcon_tv0_in: port@0 { 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 reg = <0>; 1148 1149 tcon_tv0_in_tcon_top_mixer0: endpoint@0 { 1150 reg = <0>; 1151 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; 1152 }; 1153 1154 tcon_tv0_in_tcon_top_mixer1: endpoint@1 { 1155 reg = <1>; 1156 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; 1157 }; 1158 }; 1159 1160 tcon_tv0_out: port@1 { 1161 #address-cells = <1>; 1162 #size-cells = <0>; 1163 reg = <1>; 1164 1165 tcon_tv0_out_tcon_top: endpoint@1 { 1166 reg = <1>; 1167 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; 1168 }; 1169 }; 1170 }; 1171 }; 1172 1173 tcon_tv1: lcd-controller@1c74000 { 1174 compatible = "allwinner,sun8i-r40-tcon-tv"; 1175 reg = <0x01c74000 0x1000>; 1176 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1177 clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>; 1178 clock-names = "ahb", "tcon-ch1"; 1179 resets = <&ccu RST_BUS_TCON_TV1>; 1180 reset-names = "lcd"; 1181 status = "disabled"; 1182 1183 ports { 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 1187 tcon_tv1_in: port@0 { 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 reg = <0>; 1191 1192 tcon_tv1_in_tcon_top_mixer0: endpoint@0 { 1193 reg = <0>; 1194 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>; 1195 }; 1196 1197 tcon_tv1_in_tcon_top_mixer1: endpoint@1 { 1198 reg = <1>; 1199 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>; 1200 }; 1201 }; 1202 1203 tcon_tv1_out: port@1 { 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 reg = <1>; 1207 1208 tcon_tv1_out_tcon_top: endpoint@1 { 1209 reg = <1>; 1210 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>; 1211 }; 1212 }; 1213 }; 1214 }; 1215 1216 gic: interrupt-controller@1c81000 { 1217 compatible = "arm,gic-400"; 1218 reg = <0x01c81000 0x1000>, 1219 <0x01c82000 0x2000>, 1220 <0x01c84000 0x2000>, 1221 <0x01c86000 0x2000>; 1222 interrupt-controller; 1223 #interrupt-cells = <3>; 1224 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1225 }; 1226 1227 hdmi: hdmi@1ee0000 { 1228 compatible = "allwinner,sun8i-r40-dw-hdmi", 1229 "allwinner,sun8i-a83t-dw-hdmi"; 1230 reg = <0x01ee0000 0x10000>; 1231 reg-io-width = <1>; 1232 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1233 clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, 1234 <&ccu CLK_HDMI>, <&rtc 0>; 1235 clock-names = "iahb", "isfr", "tmds", "cec"; 1236 resets = <&ccu RST_BUS_HDMI1>; 1237 reset-names = "ctrl"; 1238 phys = <&hdmi_phy>; 1239 phy-names = "phy"; 1240 status = "disabled"; 1241 1242 ports { 1243 #address-cells = <1>; 1244 #size-cells = <0>; 1245 1246 hdmi_in: port@0 { 1247 reg = <0>; 1248 1249 hdmi_in_tcon_top: endpoint { 1250 remote-endpoint = <&tcon_top_hdmi_out_hdmi>; 1251 }; 1252 }; 1253 1254 hdmi_out: port@1 { 1255 reg = <1>; 1256 }; 1257 }; 1258 }; 1259 1260 hdmi_phy: hdmi-phy@1ef0000 { 1261 compatible = "allwinner,sun8i-r40-hdmi-phy"; 1262 reg = <0x01ef0000 0x10000>; 1263 clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>, 1264 <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>; 1265 clock-names = "bus", "mod", "pll-0", "pll-1"; 1266 resets = <&ccu RST_BUS_HDMI0>; 1267 reset-names = "phy"; 1268 #phy-cells = <0>; 1269 }; 1270 }; 1271 1272 pmu { 1273 compatible = "arm,cortex-a7-pmu"; 1274 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1277 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1278 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 1279 }; 1280 1281 timer { 1282 compatible = "arm,armv7-timer"; 1283 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1284 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1285 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1286 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1287 }; 1288};