cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sun8i-v3.dtsi (1242B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
      4 * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
      5 */
      6
      7#include "sun8i-v3s.dtsi"
      8
      9/ {
     10	soc {
     11		i2s0: i2s@1c22000 {
     12			#sound-dai-cells = <0>;
     13			compatible = "allwinner,sun8i-v3-i2s",
     14				     "allwinner,sun8i-h3-i2s";
     15			reg = <0x01c22000 0x400>;
     16			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
     17			clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
     18			clock-names = "apb", "mod";
     19			dmas = <&dma 3>, <&dma 3>;
     20			dma-names = "rx", "tx";
     21			pinctrl-names = "default";
     22			pinctrl-0 = <&i2s0_pins>;
     23			resets = <&ccu RST_BUS_I2S0>;
     24			status = "disabled";
     25		};
     26	};
     27};
     28
     29&ccu {
     30	compatible = "allwinner,sun8i-v3-ccu";
     31};
     32
     33&codec_analog {
     34	compatible = "allwinner,sun8i-v3-codec-analog",
     35		     "allwinner,sun8i-h3-codec-analog";
     36};
     37
     38&emac {
     39	/delete-property/ phy-handle;
     40	/delete-property/ phy-mode;
     41};
     42
     43&mdio_mux {
     44	external_mdio: mdio@2 {
     45		reg = <2>;
     46		#address-cells = <1>;
     47		#size-cells = <0>;
     48	};
     49};
     50
     51&pio {
     52	compatible = "allwinner,sun8i-v3-pinctrl";
     53
     54	i2s0_pins: i2s0-pins {
     55		pins = "PG10", "PG11", "PG12", "PG13";
     56		function = "i2s";
     57	};
     58
     59	uart1_pg_pins: uart1-pg-pins {
     60		pins = "PG6", "PG7";
     61		function = "uart1";
     62	};
     63};