sunxi-h3-h5.dtsi (25546B)
1/* 2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/sun8i-de2.h> 44#include <dt-bindings/clock/sun8i-h3-ccu.h> 45#include <dt-bindings/clock/sun8i-r-ccu.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/reset/sun8i-de2.h> 48#include <dt-bindings/reset/sun8i-h3-ccu.h> 49#include <dt-bindings/reset/sun8i-r-ccu.h> 50 51/ { 52 interrupt-parent = <&gic>; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 56 chosen { 57 #address-cells = <1>; 58 #size-cells = <1>; 59 ranges; 60 61 framebuffer-hdmi { 62 compatible = "allwinner,simple-framebuffer", 63 "simple-framebuffer"; 64 allwinner,pipeline = "mixer0-lcd0-hdmi"; 65 clocks = <&display_clocks CLK_MIXER0>, 66 <&ccu CLK_TCON0>, <&ccu CLK_HDMI>; 67 status = "disabled"; 68 }; 69 70 framebuffer-tve { 71 compatible = "allwinner,simple-framebuffer", 72 "simple-framebuffer"; 73 allwinner,pipeline = "mixer1-lcd1-tve"; 74 clocks = <&display_clocks CLK_MIXER1>, 75 <&ccu CLK_TVE>; 76 status = "disabled"; 77 }; 78 }; 79 80 clocks { 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges; 84 85 osc24M: osc24M_clk { 86 #clock-cells = <0>; 87 compatible = "fixed-clock"; 88 clock-frequency = <24000000>; 89 clock-accuracy = <50000>; 90 clock-output-names = "osc24M"; 91 }; 92 93 osc32k: osc32k_clk { 94 #clock-cells = <0>; 95 compatible = "fixed-clock"; 96 clock-frequency = <32768>; 97 clock-accuracy = <50000>; 98 clock-output-names = "ext_osc32k"; 99 }; 100 }; 101 102 de: display-engine { 103 compatible = "allwinner,sun8i-h3-display-engine"; 104 allwinner,pipelines = <&mixer0>; 105 status = "disabled"; 106 }; 107 108 soc { 109 compatible = "simple-bus"; 110 #address-cells = <1>; 111 #size-cells = <1>; 112 dma-ranges; 113 ranges; 114 115 display_clocks: clock@1000000 { 116 /* compatible is in per SoC .dtsi file */ 117 reg = <0x01000000 0x10000>; 118 clocks = <&ccu CLK_BUS_DE>, 119 <&ccu CLK_DE>; 120 clock-names = "bus", 121 "mod"; 122 resets = <&ccu RST_BUS_DE>; 123 #clock-cells = <1>; 124 #reset-cells = <1>; 125 }; 126 127 mixer0: mixer@1100000 { 128 compatible = "allwinner,sun8i-h3-de2-mixer-0"; 129 reg = <0x01100000 0x100000>; 130 clocks = <&display_clocks CLK_BUS_MIXER0>, 131 <&display_clocks CLK_MIXER0>; 132 clock-names = "bus", 133 "mod"; 134 resets = <&display_clocks RST_MIXER0>; 135 136 ports { 137 #address-cells = <1>; 138 #size-cells = <0>; 139 140 mixer0_out: port@1 { 141 reg = <1>; 142 143 mixer0_out_tcon0: endpoint { 144 remote-endpoint = <&tcon0_in_mixer0>; 145 }; 146 }; 147 }; 148 }; 149 150 dma: dma-controller@1c02000 { 151 compatible = "allwinner,sun8i-h3-dma"; 152 reg = <0x01c02000 0x1000>; 153 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&ccu CLK_BUS_DMA>; 155 resets = <&ccu RST_BUS_DMA>; 156 #dma-cells = <1>; 157 }; 158 159 tcon0: lcd-controller@1c0c000 { 160 compatible = "allwinner,sun8i-h3-tcon-tv", 161 "allwinner,sun8i-a83t-tcon-tv"; 162 reg = <0x01c0c000 0x1000>; 163 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 164 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 165 clock-names = "ahb", "tcon-ch1"; 166 resets = <&ccu RST_BUS_TCON0>; 167 reset-names = "lcd"; 168 169 ports { 170 #address-cells = <1>; 171 #size-cells = <0>; 172 173 tcon0_in: port@0 { 174 reg = <0>; 175 176 tcon0_in_mixer0: endpoint { 177 remote-endpoint = <&mixer0_out_tcon0>; 178 }; 179 }; 180 181 tcon0_out: port@1 { 182 #address-cells = <1>; 183 #size-cells = <0>; 184 reg = <1>; 185 186 tcon0_out_hdmi: endpoint@1 { 187 reg = <1>; 188 remote-endpoint = <&hdmi_in_tcon0>; 189 }; 190 }; 191 }; 192 }; 193 194 mmc0: mmc@1c0f000 { 195 /* compatible and clocks are in per SoC .dtsi file */ 196 reg = <0x01c0f000 0x1000>; 197 pinctrl-names = "default"; 198 pinctrl-0 = <&mmc0_pins>; 199 resets = <&ccu RST_BUS_MMC0>; 200 reset-names = "ahb"; 201 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 202 status = "disabled"; 203 #address-cells = <1>; 204 #size-cells = <0>; 205 }; 206 207 mmc1: mmc@1c10000 { 208 /* compatible and clocks are in per SoC .dtsi file */ 209 reg = <0x01c10000 0x1000>; 210 pinctrl-names = "default"; 211 pinctrl-0 = <&mmc1_pins>; 212 resets = <&ccu RST_BUS_MMC1>; 213 reset-names = "ahb"; 214 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 215 status = "disabled"; 216 #address-cells = <1>; 217 #size-cells = <0>; 218 }; 219 220 mmc2: mmc@1c11000 { 221 /* compatible and clocks are in per SoC .dtsi file */ 222 reg = <0x01c11000 0x1000>; 223 resets = <&ccu RST_BUS_MMC2>; 224 reset-names = "ahb"; 225 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 226 status = "disabled"; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 }; 230 231 sid: eeprom@1c14000 { 232 /* compatible is in per SoC .dtsi file */ 233 reg = <0x1c14000 0x400>; 234 #address-cells = <1>; 235 #size-cells = <1>; 236 237 ths_calibration: thermal-sensor-calibration@34 { 238 reg = <0x34 4>; 239 }; 240 }; 241 242 msgbox: mailbox@1c17000 { 243 compatible = "allwinner,sun8i-h3-msgbox", 244 "allwinner,sun6i-a31-msgbox"; 245 reg = <0x01c17000 0x1000>; 246 clocks = <&ccu CLK_BUS_MSGBOX>; 247 resets = <&ccu RST_BUS_MSGBOX>; 248 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 249 #mbox-cells = <1>; 250 }; 251 252 usb_otg: usb@1c19000 { 253 compatible = "allwinner,sun8i-h3-musb"; 254 reg = <0x01c19000 0x400>; 255 clocks = <&ccu CLK_BUS_OTG>; 256 resets = <&ccu RST_BUS_OTG>; 257 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 258 interrupt-names = "mc"; 259 phys = <&usbphy 0>; 260 phy-names = "usb"; 261 extcon = <&usbphy 0>; 262 dr_mode = "otg"; 263 status = "disabled"; 264 }; 265 266 usbphy: phy@1c19400 { 267 compatible = "allwinner,sun8i-h3-usb-phy"; 268 reg = <0x01c19400 0x2c>, 269 <0x01c1a800 0x4>, 270 <0x01c1b800 0x4>, 271 <0x01c1c800 0x4>, 272 <0x01c1d800 0x4>; 273 reg-names = "phy_ctrl", 274 "pmu0", 275 "pmu1", 276 "pmu2", 277 "pmu3"; 278 clocks = <&ccu CLK_USB_PHY0>, 279 <&ccu CLK_USB_PHY1>, 280 <&ccu CLK_USB_PHY2>, 281 <&ccu CLK_USB_PHY3>; 282 clock-names = "usb0_phy", 283 "usb1_phy", 284 "usb2_phy", 285 "usb3_phy"; 286 resets = <&ccu RST_USB_PHY0>, 287 <&ccu RST_USB_PHY1>, 288 <&ccu RST_USB_PHY2>, 289 <&ccu RST_USB_PHY3>; 290 reset-names = "usb0_reset", 291 "usb1_reset", 292 "usb2_reset", 293 "usb3_reset"; 294 status = "disabled"; 295 #phy-cells = <1>; 296 }; 297 298 ehci0: usb@1c1a000 { 299 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 300 reg = <0x01c1a000 0x100>; 301 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; 303 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; 304 status = "disabled"; 305 }; 306 307 ohci0: usb@1c1a400 { 308 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 309 reg = <0x01c1a400 0x100>; 310 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, 312 <&ccu CLK_USB_OHCI0>; 313 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; 314 status = "disabled"; 315 }; 316 317 ehci1: usb@1c1b000 { 318 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 319 reg = <0x01c1b000 0x100>; 320 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>; 322 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; 323 phys = <&usbphy 1>; 324 phy-names = "usb"; 325 status = "disabled"; 326 }; 327 328 ohci1: usb@1c1b400 { 329 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 330 reg = <0x01c1b400 0x100>; 331 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>, 333 <&ccu CLK_USB_OHCI1>; 334 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; 335 phys = <&usbphy 1>; 336 phy-names = "usb"; 337 status = "disabled"; 338 }; 339 340 ehci2: usb@1c1c000 { 341 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 342 reg = <0x01c1c000 0x100>; 343 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>; 345 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; 346 phys = <&usbphy 2>; 347 phy-names = "usb"; 348 status = "disabled"; 349 }; 350 351 ohci2: usb@1c1c400 { 352 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 353 reg = <0x01c1c400 0x100>; 354 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>, 356 <&ccu CLK_USB_OHCI2>; 357 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; 358 phys = <&usbphy 2>; 359 phy-names = "usb"; 360 status = "disabled"; 361 }; 362 363 ehci3: usb@1c1d000 { 364 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 365 reg = <0x01c1d000 0x100>; 366 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>; 368 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; 369 phys = <&usbphy 3>; 370 phy-names = "usb"; 371 status = "disabled"; 372 }; 373 374 ohci3: usb@1c1d400 { 375 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 376 reg = <0x01c1d400 0x100>; 377 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>, 379 <&ccu CLK_USB_OHCI3>; 380 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; 381 phys = <&usbphy 3>; 382 phy-names = "usb"; 383 status = "disabled"; 384 }; 385 386 ccu: clock@1c20000 { 387 /* compatible is in per SoC .dtsi file */ 388 reg = <0x01c20000 0x400>; 389 clocks = <&osc24M>, <&rtc 0>; 390 clock-names = "hosc", "losc"; 391 #clock-cells = <1>; 392 #reset-cells = <1>; 393 }; 394 395 pio: pinctrl@1c20800 { 396 /* compatible is in per SoC .dtsi file */ 397 reg = <0x01c20800 0x400>; 398 interrupt-parent = <&r_intc>; 399 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 402 clock-names = "apb", "hosc", "losc"; 403 gpio-controller; 404 #gpio-cells = <3>; 405 interrupt-controller; 406 #interrupt-cells = <3>; 407 408 csi_pins: csi-pins { 409 pins = "PE0", "PE2", "PE3", "PE4", "PE5", 410 "PE6", "PE7", "PE8", "PE9", "PE10", 411 "PE11"; 412 function = "csi"; 413 }; 414 415 emac_rgmii_pins: emac-rgmii-pins { 416 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 417 "PD5", "PD7", "PD8", "PD9", "PD10", 418 "PD12", "PD13", "PD15", "PD16", "PD17"; 419 function = "emac"; 420 drive-strength = <40>; 421 }; 422 423 i2c0_pins: i2c0-pins { 424 pins = "PA11", "PA12"; 425 function = "i2c0"; 426 }; 427 428 i2c1_pins: i2c1-pins { 429 pins = "PA18", "PA19"; 430 function = "i2c1"; 431 }; 432 433 i2c2_pins: i2c2-pins { 434 pins = "PE12", "PE13"; 435 function = "i2c2"; 436 }; 437 438 mmc0_pins: mmc0-pins { 439 pins = "PF0", "PF1", "PF2", "PF3", 440 "PF4", "PF5"; 441 function = "mmc0"; 442 drive-strength = <30>; 443 bias-pull-up; 444 }; 445 446 mmc1_pins: mmc1-pins { 447 pins = "PG0", "PG1", "PG2", "PG3", 448 "PG4", "PG5"; 449 function = "mmc1"; 450 drive-strength = <30>; 451 bias-pull-up; 452 }; 453 454 mmc2_8bit_pins: mmc2-8bit-pins { 455 pins = "PC5", "PC6", "PC8", 456 "PC9", "PC10", "PC11", 457 "PC12", "PC13", "PC14", 458 "PC15", "PC16"; 459 function = "mmc2"; 460 drive-strength = <30>; 461 bias-pull-up; 462 }; 463 464 spdif_tx_pin: spdif-tx-pin { 465 pins = "PA17"; 466 function = "spdif"; 467 }; 468 469 spi0_pins: spi0-pins { 470 pins = "PC0", "PC1", "PC2", "PC3"; 471 function = "spi0"; 472 }; 473 474 spi1_pins: spi1-pins { 475 pins = "PA15", "PA16", "PA14", "PA13"; 476 function = "spi1"; 477 }; 478 479 uart0_pa_pins: uart0-pa-pins { 480 pins = "PA4", "PA5"; 481 function = "uart0"; 482 }; 483 484 uart1_pins: uart1-pins { 485 pins = "PG6", "PG7"; 486 function = "uart1"; 487 }; 488 489 uart1_rts_cts_pins: uart1-rts-cts-pins { 490 pins = "PG8", "PG9"; 491 function = "uart1"; 492 }; 493 494 uart2_pins: uart2-pins { 495 pins = "PA0", "PA1"; 496 function = "uart2"; 497 }; 498 499 uart2_rts_cts_pins: uart2-rts-cts-pins { 500 pins = "PA2", "PA3"; 501 function = "uart2"; 502 }; 503 504 uart3_pins: uart3-pins { 505 pins = "PA13", "PA14"; 506 function = "uart3"; 507 }; 508 509 uart3_rts_cts_pins: uart3-rts-cts-pins { 510 pins = "PA15", "PA16"; 511 function = "uart3"; 512 }; 513 }; 514 515 timer@1c20c00 { 516 compatible = "allwinner,sun8i-a23-timer"; 517 reg = <0x01c20c00 0xa0>; 518 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&osc24M>; 521 }; 522 523 emac: ethernet@1c30000 { 524 compatible = "allwinner,sun8i-h3-emac"; 525 syscon = <&syscon>; 526 reg = <0x01c30000 0x10000>; 527 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 528 interrupt-names = "macirq"; 529 resets = <&ccu RST_BUS_EMAC>; 530 reset-names = "stmmaceth"; 531 clocks = <&ccu CLK_BUS_EMAC>; 532 clock-names = "stmmaceth"; 533 status = "disabled"; 534 535 mdio: mdio { 536 #address-cells = <1>; 537 #size-cells = <0>; 538 compatible = "snps,dwmac-mdio"; 539 }; 540 541 mdio-mux { 542 compatible = "allwinner,sun8i-h3-mdio-mux"; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 546 mdio-parent-bus = <&mdio>; 547 /* Only one MDIO is usable at the time */ 548 internal_mdio: mdio@1 { 549 compatible = "allwinner,sun8i-h3-mdio-internal"; 550 reg = <1>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 554 int_mii_phy: ethernet-phy@1 { 555 compatible = "ethernet-phy-ieee802.3-c22"; 556 reg = <1>; 557 clocks = <&ccu CLK_BUS_EPHY>; 558 resets = <&ccu RST_BUS_EPHY>; 559 }; 560 }; 561 562 external_mdio: mdio@2 { 563 reg = <2>; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 }; 567 }; 568 }; 569 570 mbus: dram-controller@1c62000 { 571 /* compatible is in per SoC .dtsi file */ 572 reg = <0x01c62000 0x1000>, 573 <0x01c63000 0x1000>; 574 reg-names = "mbus", "dram"; 575 clocks = <&ccu CLK_MBUS>, 576 <&ccu CLK_DRAM>, 577 <&ccu CLK_BUS_DRAM>; 578 clock-names = "mbus", "dram", "bus"; 579 #address-cells = <1>; 580 #size-cells = <1>; 581 dma-ranges = <0x00000000 0x40000000 0xc0000000>; 582 #interconnect-cells = <1>; 583 }; 584 585 spi0: spi@1c68000 { 586 compatible = "allwinner,sun8i-h3-spi"; 587 reg = <0x01c68000 0x1000>; 588 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 590 clock-names = "ahb", "mod"; 591 dmas = <&dma 23>, <&dma 23>; 592 dma-names = "rx", "tx"; 593 pinctrl-names = "default"; 594 pinctrl-0 = <&spi0_pins>; 595 resets = <&ccu RST_BUS_SPI0>; 596 status = "disabled"; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 }; 600 601 spi1: spi@1c69000 { 602 compatible = "allwinner,sun8i-h3-spi"; 603 reg = <0x01c69000 0x1000>; 604 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 606 clock-names = "ahb", "mod"; 607 dmas = <&dma 24>, <&dma 24>; 608 dma-names = "rx", "tx"; 609 pinctrl-names = "default"; 610 pinctrl-0 = <&spi1_pins>; 611 resets = <&ccu RST_BUS_SPI1>; 612 status = "disabled"; 613 #address-cells = <1>; 614 #size-cells = <0>; 615 }; 616 617 wdt0: watchdog@1c20ca0 { 618 compatible = "allwinner,sun6i-a31-wdt"; 619 reg = <0x01c20ca0 0x20>; 620 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&osc24M>; 622 }; 623 624 spdif: spdif@1c21000 { 625 #sound-dai-cells = <0>; 626 compatible = "allwinner,sun8i-h3-spdif"; 627 reg = <0x01c21000 0x400>; 628 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 630 resets = <&ccu RST_BUS_SPDIF>; 631 clock-names = "apb", "spdif"; 632 dmas = <&dma 2>; 633 dma-names = "tx"; 634 status = "disabled"; 635 }; 636 637 pwm: pwm@1c21400 { 638 compatible = "allwinner,sun8i-h3-pwm"; 639 reg = <0x01c21400 0x8>; 640 clocks = <&osc24M>; 641 #pwm-cells = <3>; 642 status = "disabled"; 643 }; 644 645 i2s0: i2s@1c22000 { 646 #sound-dai-cells = <0>; 647 compatible = "allwinner,sun8i-h3-i2s"; 648 reg = <0x01c22000 0x400>; 649 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 651 clock-names = "apb", "mod"; 652 dmas = <&dma 3>, <&dma 3>; 653 resets = <&ccu RST_BUS_I2S0>; 654 dma-names = "rx", "tx"; 655 status = "disabled"; 656 }; 657 658 i2s1: i2s@1c22400 { 659 #sound-dai-cells = <0>; 660 compatible = "allwinner,sun8i-h3-i2s"; 661 reg = <0x01c22400 0x400>; 662 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 664 clock-names = "apb", "mod"; 665 dmas = <&dma 4>, <&dma 4>; 666 resets = <&ccu RST_BUS_I2S1>; 667 dma-names = "rx", "tx"; 668 status = "disabled"; 669 }; 670 671 i2s2: i2s@1c22800 { 672 #sound-dai-cells = <0>; 673 compatible = "allwinner,sun8i-h3-i2s"; 674 reg = <0x01c22800 0x400>; 675 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; 677 clock-names = "apb", "mod"; 678 dmas = <&dma 27>; 679 resets = <&ccu RST_BUS_I2S2>; 680 dma-names = "tx"; 681 status = "disabled"; 682 }; 683 684 codec: codec@1c22c00 { 685 #sound-dai-cells = <0>; 686 compatible = "allwinner,sun8i-h3-codec"; 687 reg = <0x01c22c00 0x400>; 688 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 690 clock-names = "apb", "codec"; 691 resets = <&ccu RST_BUS_CODEC>; 692 dmas = <&dma 15>, <&dma 15>; 693 dma-names = "rx", "tx"; 694 allwinner,codec-analog-controls = <&codec_analog>; 695 status = "disabled"; 696 }; 697 698 uart0: serial@1c28000 { 699 compatible = "snps,dw-apb-uart"; 700 reg = <0x01c28000 0x400>; 701 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 702 reg-shift = <2>; 703 reg-io-width = <4>; 704 clocks = <&ccu CLK_BUS_UART0>; 705 resets = <&ccu RST_BUS_UART0>; 706 dmas = <&dma 6>, <&dma 6>; 707 dma-names = "rx", "tx"; 708 status = "disabled"; 709 }; 710 711 uart1: serial@1c28400 { 712 compatible = "snps,dw-apb-uart"; 713 reg = <0x01c28400 0x400>; 714 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 715 reg-shift = <2>; 716 reg-io-width = <4>; 717 clocks = <&ccu CLK_BUS_UART1>; 718 resets = <&ccu RST_BUS_UART1>; 719 dmas = <&dma 7>, <&dma 7>; 720 dma-names = "rx", "tx"; 721 status = "disabled"; 722 }; 723 724 uart2: serial@1c28800 { 725 compatible = "snps,dw-apb-uart"; 726 reg = <0x01c28800 0x400>; 727 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 728 reg-shift = <2>; 729 reg-io-width = <4>; 730 clocks = <&ccu CLK_BUS_UART2>; 731 resets = <&ccu RST_BUS_UART2>; 732 dmas = <&dma 8>, <&dma 8>; 733 dma-names = "rx", "tx"; 734 status = "disabled"; 735 }; 736 737 uart3: serial@1c28c00 { 738 compatible = "snps,dw-apb-uart"; 739 reg = <0x01c28c00 0x400>; 740 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 741 reg-shift = <2>; 742 reg-io-width = <4>; 743 clocks = <&ccu CLK_BUS_UART3>; 744 resets = <&ccu RST_BUS_UART3>; 745 dmas = <&dma 9>, <&dma 9>; 746 dma-names = "rx", "tx"; 747 status = "disabled"; 748 }; 749 750 i2c0: i2c@1c2ac00 { 751 compatible = "allwinner,sun6i-a31-i2c"; 752 reg = <0x01c2ac00 0x400>; 753 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&ccu CLK_BUS_I2C0>; 755 resets = <&ccu RST_BUS_I2C0>; 756 pinctrl-names = "default"; 757 pinctrl-0 = <&i2c0_pins>; 758 status = "disabled"; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 }; 762 763 i2c1: i2c@1c2b000 { 764 compatible = "allwinner,sun6i-a31-i2c"; 765 reg = <0x01c2b000 0x400>; 766 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&ccu CLK_BUS_I2C1>; 768 resets = <&ccu RST_BUS_I2C1>; 769 pinctrl-names = "default"; 770 pinctrl-0 = <&i2c1_pins>; 771 status = "disabled"; 772 #address-cells = <1>; 773 #size-cells = <0>; 774 }; 775 776 i2c2: i2c@1c2b400 { 777 compatible = "allwinner,sun6i-a31-i2c"; 778 reg = <0x01c2b400 0x400>; 779 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&ccu CLK_BUS_I2C2>; 781 resets = <&ccu RST_BUS_I2C2>; 782 pinctrl-names = "default"; 783 pinctrl-0 = <&i2c2_pins>; 784 status = "disabled"; 785 #address-cells = <1>; 786 #size-cells = <0>; 787 }; 788 789 gic: interrupt-controller@1c81000 { 790 compatible = "arm,gic-400"; 791 reg = <0x01c81000 0x1000>, 792 <0x01c82000 0x2000>, 793 <0x01c84000 0x2000>, 794 <0x01c86000 0x2000>; 795 interrupt-controller; 796 #interrupt-cells = <3>; 797 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 798 }; 799 800 csi: camera@1cb0000 { 801 compatible = "allwinner,sun8i-h3-csi"; 802 reg = <0x01cb0000 0x1000>; 803 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&ccu CLK_BUS_CSI>, 805 <&ccu CLK_CSI_SCLK>, 806 <&ccu CLK_DRAM_CSI>; 807 clock-names = "bus", "mod", "ram"; 808 resets = <&ccu RST_BUS_CSI>; 809 pinctrl-names = "default"; 810 pinctrl-0 = <&csi_pins>; 811 status = "disabled"; 812 }; 813 814 hdmi: hdmi@1ee0000 { 815 compatible = "allwinner,sun8i-h3-dw-hdmi", 816 "allwinner,sun8i-a83t-dw-hdmi"; 817 reg = <0x01ee0000 0x10000>; 818 reg-io-width = <1>; 819 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 821 <&ccu CLK_HDMI>, <&rtc 0>; 822 clock-names = "iahb", "isfr", "tmds", "cec"; 823 resets = <&ccu RST_BUS_HDMI1>; 824 reset-names = "ctrl"; 825 phys = <&hdmi_phy>; 826 phy-names = "phy"; 827 status = "disabled"; 828 829 ports { 830 #address-cells = <1>; 831 #size-cells = <0>; 832 833 hdmi_in: port@0 { 834 reg = <0>; 835 836 hdmi_in_tcon0: endpoint { 837 remote-endpoint = <&tcon0_out_hdmi>; 838 }; 839 }; 840 841 hdmi_out: port@1 { 842 reg = <1>; 843 }; 844 }; 845 }; 846 847 hdmi_phy: hdmi-phy@1ef0000 { 848 compatible = "allwinner,sun8i-h3-hdmi-phy"; 849 reg = <0x01ef0000 0x10000>; 850 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 851 <&ccu CLK_PLL_VIDEO>; 852 clock-names = "bus", "mod", "pll-0"; 853 resets = <&ccu RST_BUS_HDMI0>; 854 reset-names = "phy"; 855 #phy-cells = <0>; 856 }; 857 858 rtc: rtc@1f00000 { 859 /* compatible is in per SoC .dtsi file */ 860 reg = <0x01f00000 0x400>; 861 interrupt-parent = <&r_intc>; 862 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 864 clock-output-names = "osc32k", "osc32k-out", "iosc"; 865 clocks = <&osc32k>; 866 #clock-cells = <1>; 867 }; 868 869 r_intc: interrupt-controller@1f00c00 { 870 compatible = "allwinner,sun8i-h3-r-intc", 871 "allwinner,sun6i-a31-r-intc"; 872 interrupt-controller; 873 #interrupt-cells = <3>; 874 reg = <0x01f00c00 0x400>; 875 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 876 }; 877 878 r_ccu: clock@1f01400 { 879 compatible = "allwinner,sun8i-h3-r-ccu"; 880 reg = <0x01f01400 0x100>; 881 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 882 <&ccu CLK_PLL_PERIPH0>; 883 clock-names = "hosc", "losc", "iosc", "pll-periph"; 884 #clock-cells = <1>; 885 #reset-cells = <1>; 886 }; 887 888 codec_analog: codec-analog@1f015c0 { 889 compatible = "allwinner,sun8i-h3-codec-analog"; 890 reg = <0x01f015c0 0x4>; 891 }; 892 893 ir: ir@1f02000 { 894 compatible = "allwinner,sun6i-a31-ir"; 895 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 896 clock-names = "apb", "ir"; 897 resets = <&r_ccu RST_APB0_IR>; 898 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 899 reg = <0x01f02000 0x400>; 900 status = "disabled"; 901 }; 902 903 r_i2c: i2c@1f02400 { 904 compatible = "allwinner,sun6i-a31-i2c"; 905 reg = <0x01f02400 0x400>; 906 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 907 pinctrl-names = "default"; 908 pinctrl-0 = <&r_i2c_pins>; 909 clocks = <&r_ccu CLK_APB0_I2C>; 910 resets = <&r_ccu RST_APB0_I2C>; 911 status = "disabled"; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 }; 915 916 r_uart: serial@1f02800 { 917 compatible = "snps,dw-apb-uart"; 918 reg = <0x01f02800 0x400>; 919 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 920 reg-shift = <2>; 921 reg-io-width = <4>; 922 clocks = <&r_ccu CLK_APB0_UART>; 923 resets = <&r_ccu RST_APB0_UART>; 924 pinctrl-names = "default"; 925 pinctrl-0 = <&r_uart_pins>; 926 status = "disabled"; 927 }; 928 929 r_pio: pinctrl@1f02c00 { 930 compatible = "allwinner,sun8i-h3-r-pinctrl"; 931 reg = <0x01f02c00 0x400>; 932 interrupt-parent = <&r_intc>; 933 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 934 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>; 935 clock-names = "apb", "hosc", "losc"; 936 gpio-controller; 937 #gpio-cells = <3>; 938 interrupt-controller; 939 #interrupt-cells = <3>; 940 941 r_ir_rx_pin: r-ir-rx-pin { 942 pins = "PL11"; 943 function = "s_cir_rx"; 944 }; 945 946 r_i2c_pins: r-i2c-pins { 947 pins = "PL0", "PL1"; 948 function = "s_i2c"; 949 }; 950 951 r_pwm_pin: r-pwm-pin { 952 pins = "PL10"; 953 function = "s_pwm"; 954 }; 955 956 r_uart_pins: r-uart-pins { 957 pins = "PL2", "PL3"; 958 function = "s_uart"; 959 }; 960 }; 961 962 r_pwm: pwm@1f03800 { 963 compatible = "allwinner,sun8i-h3-pwm"; 964 reg = <0x01f03800 0x8>; 965 pinctrl-names = "default"; 966 pinctrl-0 = <&r_pwm_pin>; 967 clocks = <&osc24M>; 968 #pwm-cells = <3>; 969 status = "disabled"; 970 }; 971 }; 972};