cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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tegra124-apalis.dtsi (57994B)


      1// SPDX-License-Identifier: GPL-2.0 OR X11
      2/*
      3 * Copyright 2016-2019 Toradex AG
      4 */
      5
      6#include "tegra124.dtsi"
      7#include "tegra124-apalis-emc.dtsi"
      8
      9/*
     10 * Toradex Apalis TK1 Module Device Tree
     11 * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A
     12 */
     13/ {
     14	memory@80000000 {
     15		reg = <0x0 0x80000000 0x0 0x80000000>;
     16	};
     17
     18	pcie@1003000 {
     19		status = "okay";
     20		avddio-pex-supply = <&reg_1v05_vdd>;
     21		avdd-pex-pll-supply = <&reg_1v05_vdd>;
     22		avdd-pll-erefe-supply = <&reg_1v05_avdd>;
     23		dvddio-pex-supply = <&reg_1v05_vdd>;
     24		hvdd-pex-pll-e-supply = <&reg_module_3v3>;
     25		hvdd-pex-supply = <&reg_module_3v3>;
     26		vddio-pex-ctl-supply = <&reg_module_3v3>;
     27
     28		/* Apalis PCIe (additional lane Apalis type specific) */
     29		pci@1,0 {
     30			/* PCIE1_RX/TX and TS_DIFF1/2 */
     31			phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>,
     32			       <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
     33			phy-names = "pcie-0", "pcie-1";
     34		};
     35
     36		/* I210 Gigabit Ethernet Controller (On-module) */
     37		pci@2,0 {
     38			phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
     39			phy-names = "pcie-0";
     40			status = "okay";
     41
     42			ethernet@0,0 {
     43				reg = <0 0 0 0 0>;
     44				local-mac-address = [00 00 00 00 00 00];
     45			};
     46		};
     47	};
     48
     49	host1x@50000000 {
     50		hdmi@54280000 {
     51			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
     52			nvidia,hpd-gpio =
     53				<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
     54			pll-supply = <&reg_1v05_avdd_hdmi_pll>;
     55			vdd-supply = <&reg_3v3_avdd_hdmi>;
     56		};
     57	};
     58
     59	gpu@57000000 {
     60		/*
     61		 * Node left disabled on purpose - the bootloader will enable
     62		 * it after having set the VPR up
     63		 */
     64		vdd-supply = <&reg_vdd_gpu>;
     65	};
     66
     67	pinmux@70000868 {
     68		pinctrl-names = "default";
     69		pinctrl-0 = <&state_default>;
     70
     71		state_default: pinmux {
     72			/* Analogue Audio (On-module) */
     73			dap3-fs-pp0 {
     74				nvidia,pins = "dap3_fs_pp0";
     75				nvidia,function = "i2s2";
     76				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
     77				nvidia,tristate = <TEGRA_PIN_DISABLE>;
     78				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
     79			};
     80			dap3-din-pp1 {
     81				nvidia,pins = "dap3_din_pp1";
     82				nvidia,function = "i2s2";
     83				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
     84				nvidia,tristate = <TEGRA_PIN_ENABLE>;
     85				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
     86			};
     87			dap3-dout-pp2 {
     88				nvidia,pins = "dap3_dout_pp2";
     89				nvidia,function = "i2s2";
     90				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
     91				nvidia,tristate = <TEGRA_PIN_DISABLE>;
     92				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
     93			};
     94			dap3-sclk-pp3 {
     95				nvidia,pins = "dap3_sclk_pp3";
     96				nvidia,function = "i2s2";
     97				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
     98				nvidia,tristate = <TEGRA_PIN_DISABLE>;
     99				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    100			};
    101			dap-mclk1-pw4 {
    102				nvidia,pins = "dap_mclk1_pw4";
    103				nvidia,function = "extperiph1";
    104				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    105				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    106				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    107			};
    108
    109			/* Apalis BKL1_ON */
    110			pbb5 {
    111				nvidia,pins = "pbb5";
    112				nvidia,function = "vgp5";
    113				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    114				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    115				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    116			};
    117
    118			/* Apalis BKL1_PWM */
    119			pu6 {
    120				nvidia,pins = "pu6";
    121				nvidia,function = "pwm3";
    122				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    123				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    124				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    125			};
    126
    127			/* Apalis CAM1_MCLK */
    128			cam-mclk-pcc0 {
    129				nvidia,pins = "cam_mclk_pcc0";
    130				nvidia,function = "vi_alt3";
    131				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    132				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    133				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    134			};
    135
    136			/* Apalis Digital Audio */
    137			dap2-fs-pa2 {
    138				nvidia,pins = "dap2_fs_pa2";
    139				nvidia,function = "hda";
    140				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    141				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    142				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    143			};
    144			dap2-sclk-pa3 {
    145				nvidia,pins = "dap2_sclk_pa3";
    146				nvidia,function = "hda";
    147				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    148				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    149				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    150			};
    151			dap2-din-pa4 {
    152				nvidia,pins = "dap2_din_pa4";
    153				nvidia,function = "hda";
    154				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    155				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    156				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    157			};
    158			dap2-dout-pa5 {
    159				nvidia,pins = "dap2_dout_pa5";
    160				nvidia,function = "hda";
    161				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    162				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    163				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    164			};
    165			pbb3 { /* DAP1_RESET */
    166				nvidia,pins = "pbb3";
    167				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    168				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    169				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    170			};
    171			clk3-out-pee0 {
    172				nvidia,pins = "clk3_out_pee0";
    173				nvidia,function = "extperiph3";
    174				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    175				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    176				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    177			};
    178
    179			/* Apalis GPIO */
    180			ddc-scl-pv4 {
    181				nvidia,pins = "ddc_scl_pv4";
    182				nvidia,function = "rsvd2";
    183				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    184				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    185				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    186			};
    187			ddc-sda-pv5 {
    188				nvidia,pins = "ddc_sda_pv5";
    189				nvidia,function = "rsvd2";
    190				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    191				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    192				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    193			};
    194			pex-l0-rst-n-pdd1 {
    195				nvidia,pins = "pex_l0_rst_n_pdd1";
    196				nvidia,function = "rsvd2";
    197				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    198				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    199				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    200			};
    201			pex-l0-clkreq-n-pdd2 {
    202				nvidia,pins = "pex_l0_clkreq_n_pdd2";
    203				nvidia,function = "rsvd2";
    204				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    205				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    206				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    207			};
    208			pex-l1-rst-n-pdd5 {
    209				nvidia,pins = "pex_l1_rst_n_pdd5";
    210				nvidia,function = "rsvd2";
    211				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    212				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    213				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    214			};
    215			pex-l1-clkreq-n-pdd6 {
    216				nvidia,pins = "pex_l1_clkreq_n_pdd6";
    217				nvidia,function = "rsvd2";
    218				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    219				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    220				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    221			};
    222			dp-hpd-pff0 {
    223				nvidia,pins = "dp_hpd_pff0";
    224				nvidia,function = "dp";
    225				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    226				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    227				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    228			};
    229			pff2 {
    230				nvidia,pins = "pff2";
    231				nvidia,function = "rsvd2";
    232				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    233				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    234				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    235			};
    236			owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
    237				nvidia,pins = "owr";
    238				nvidia,function = "rsvd2";
    239				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    240				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    241				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    242				nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
    243			};
    244
    245			/* Apalis HDMI1_CEC */
    246			hdmi-cec-pee3 {
    247				nvidia,pins = "hdmi_cec_pee3";
    248				nvidia,function = "cec";
    249				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    250				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    251				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    252				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
    253			};
    254
    255			/* Apalis HDMI1_HPD */
    256			hdmi-int-pn7 {
    257				nvidia,pins = "hdmi_int_pn7";
    258				nvidia,function = "rsvd1";
    259				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
    260				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    261				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    262				nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
    263			};
    264
    265			/* Apalis I2C1 */
    266			gen1-i2c-scl-pc4 {
    267				nvidia,pins = "gen1_i2c_scl_pc4";
    268				nvidia,function = "i2c1";
    269				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    270				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    271				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    272				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
    273			};
    274			gen1-i2c-sda-pc5 {
    275				nvidia,pins = "gen1_i2c_sda_pc5";
    276				nvidia,function = "i2c1";
    277				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    278				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    279				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    280				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
    281			};
    282
    283			/* Apalis I2C2 (DDC) */
    284			gen2-i2c-scl-pt5 {
    285				nvidia,pins = "gen2_i2c_scl_pt5";
    286				nvidia,function = "i2c2";
    287				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    288				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    289				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    290				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
    291			};
    292			gen2-i2c-sda-pt6 {
    293				nvidia,pins = "gen2_i2c_sda_pt6";
    294				nvidia,function = "i2c2";
    295				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    296				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    297				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    298				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
    299			};
    300
    301			/* Apalis I2C3 (CAM) */
    302			cam-i2c-scl-pbb1 {
    303				nvidia,pins = "cam_i2c_scl_pbb1";
    304				nvidia,function = "i2c3";
    305				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    306				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    307				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    308				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
    309			};
    310			cam-i2c-sda-pbb2 {
    311				nvidia,pins = "cam_i2c_sda_pbb2";
    312				nvidia,function = "i2c3";
    313				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    314				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    315				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    316				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
    317			};
    318
    319			/* Apalis MMC1 */
    320			sdmmc1-cd-n-pv3 { /* CD# GPIO */
    321				nvidia,pins = "sdmmc1_wp_n_pv3";
    322				nvidia,function = "sdmmc1";
    323				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    324				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    325				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    326			};
    327			clk2-out-pw5 { /* D5 GPIO */
    328				nvidia,pins = "clk2_out_pw5";
    329				nvidia,function = "rsvd2";
    330				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    331				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    332				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    333			};
    334			sdmmc1-dat3-py4 {
    335				nvidia,pins = "sdmmc1_dat3_py4";
    336				nvidia,function = "sdmmc1";
    337				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    338				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    339				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    340			};
    341			sdmmc1-dat2-py5 {
    342				nvidia,pins = "sdmmc1_dat2_py5";
    343				nvidia,function = "sdmmc1";
    344				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    345				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    346				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    347			};
    348			sdmmc1-dat1-py6 {
    349				nvidia,pins = "sdmmc1_dat1_py6";
    350				nvidia,function = "sdmmc1";
    351				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    352				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    353				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    354			};
    355			sdmmc1-dat0-py7 {
    356				nvidia,pins = "sdmmc1_dat0_py7";
    357				nvidia,function = "sdmmc1";
    358				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    359				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    360				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    361			};
    362			sdmmc1-clk-pz0 {
    363				nvidia,pins = "sdmmc1_clk_pz0";
    364				nvidia,function = "sdmmc1";
    365				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    366				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    367				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    368			};
    369			sdmmc1-cmd-pz1 {
    370				nvidia,pins = "sdmmc1_cmd_pz1";
    371				nvidia,function = "sdmmc1";
    372				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    373				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    374				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    375			};
    376			clk2-req-pcc5 { /* D4 GPIO */
    377				nvidia,pins = "clk2_req_pcc5";
    378				nvidia,function = "rsvd2";
    379				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    380				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    381				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    382			};
    383			sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */
    384				nvidia,pins = "sdmmc3_clk_lb_in_pee5";
    385				nvidia,function = "rsvd2";
    386				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    387				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    388				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    389			};
    390			usb-vbus-en2-pff1 { /* D7 GPIO */
    391				nvidia,pins = "usb_vbus_en2_pff1";
    392				nvidia,function = "rsvd2";
    393				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    394				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    395				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    396			};
    397
    398			/* Apalis PWM */
    399			ph0 {
    400				nvidia,pins = "ph0";
    401				nvidia,function = "pwm0";
    402				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    403				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    404				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    405			};
    406			ph1 {
    407				nvidia,pins = "ph1";
    408				nvidia,function = "pwm1";
    409				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    410				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    411				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    412			};
    413			ph2 {
    414				nvidia,pins = "ph2";
    415				nvidia,function = "pwm2";
    416				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    417				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    418				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    419			};
    420			/* PWM3 active on pu6 being Apalis BKL1_PWM as well */
    421			ph3 {
    422				nvidia,pins = "ph3";
    423				nvidia,function = "pwm3";
    424				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    425				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    426				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    427			};
    428
    429			/* Apalis SATA1_ACT# */
    430			dap1-dout-pn2 {
    431				nvidia,pins = "dap1_dout_pn2";
    432				nvidia,function = "gmi";
    433				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    434				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    435				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    436			};
    437
    438			/* Apalis SD1 */
    439			sdmmc3-clk-pa6 {
    440				nvidia,pins = "sdmmc3_clk_pa6";
    441				nvidia,function = "sdmmc3";
    442				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    443				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    444				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    445			};
    446			sdmmc3-cmd-pa7 {
    447				nvidia,pins = "sdmmc3_cmd_pa7";
    448				nvidia,function = "sdmmc3";
    449				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    450				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    451				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    452			};
    453			sdmmc3-dat3-pb4 {
    454				nvidia,pins = "sdmmc3_dat3_pb4";
    455				nvidia,function = "sdmmc3";
    456				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    457				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    458				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    459			};
    460			sdmmc3-dat2-pb5 {
    461				nvidia,pins = "sdmmc3_dat2_pb5";
    462				nvidia,function = "sdmmc3";
    463				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    464				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    465				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    466			};
    467			sdmmc3-dat1-pb6 {
    468				nvidia,pins = "sdmmc3_dat1_pb6";
    469				nvidia,function = "sdmmc3";
    470				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    471				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    472				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    473			};
    474			sdmmc3-dat0-pb7 {
    475				nvidia,pins = "sdmmc3_dat0_pb7";
    476				nvidia,function = "sdmmc3";
    477				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    478				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    479				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    480			};
    481			sdmmc3-cd-n-pv2 { /* CD# GPIO */
    482				nvidia,pins = "sdmmc3_cd_n_pv2";
    483				nvidia,function = "rsvd3";
    484				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    485				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    486				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    487			};
    488
    489			/* Apalis SPDIF */
    490			spdif-out-pk5 {
    491				nvidia,pins = "spdif_out_pk5";
    492				nvidia,function = "spdif";
    493				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    494				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    495				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    496			};
    497			spdif-in-pk6 {
    498				nvidia,pins = "spdif_in_pk6";
    499				nvidia,function = "spdif";
    500				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    501				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    502				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    503			};
    504
    505			/* Apalis SPI1 */
    506			ulpi-clk-py0 {
    507				nvidia,pins = "ulpi_clk_py0";
    508				nvidia,function = "spi1";
    509				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    510				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    511				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    512			};
    513			ulpi-dir-py1 {
    514				nvidia,pins = "ulpi_dir_py1";
    515				nvidia,function = "spi1";
    516				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    517				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    518				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    519			};
    520			ulpi-nxt-py2 {
    521				nvidia,pins = "ulpi_nxt_py2";
    522				nvidia,function = "spi1";
    523				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    524				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    525				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    526			};
    527			ulpi-stp-py3 {
    528				nvidia,pins = "ulpi_stp_py3";
    529				nvidia,function = "spi1";
    530				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    531				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    532				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    533			};
    534
    535			/* Apalis SPI2 */
    536			pg5 {
    537				nvidia,pins = "pg5";
    538				nvidia,function = "spi4";
    539				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    540				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    541				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    542			};
    543			pg6 {
    544				nvidia,pins = "pg6";
    545				nvidia,function = "spi4";
    546				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    547				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    548				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    549			};
    550			pg7 {
    551				nvidia,pins = "pg7";
    552				nvidia,function = "spi4";
    553				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    554				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    555				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    556			};
    557			pi3 {
    558				nvidia,pins = "pi3";
    559				nvidia,function = "spi4";
    560				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    561				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    562				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    563			};
    564
    565			/* Apalis UART1 */
    566			pb1 { /* DCD GPIO */
    567				nvidia,pins = "pb1";
    568				nvidia,function = "rsvd2";
    569				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    570				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    571				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    572			};
    573			pk7 { /* RI GPIO */
    574				nvidia,pins = "pk7";
    575				nvidia,function = "rsvd2";
    576				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    577				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    578				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    579			};
    580			uart1-txd-pu0 {
    581				nvidia,pins = "pu0";
    582				nvidia,function = "uarta";
    583				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    584				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    585				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    586			};
    587			uart1-rxd-pu1 {
    588				nvidia,pins = "pu1";
    589				nvidia,function = "uarta";
    590				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    591				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    592				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    593			};
    594			uart1-cts-n-pu2 {
    595				nvidia,pins = "pu2";
    596				nvidia,function = "uarta";
    597				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    598				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    599				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    600			};
    601			uart1-rts-n-pu3 {
    602				nvidia,pins = "pu3";
    603				nvidia,function = "uarta";
    604				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    605				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    606				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    607			};
    608			uart3-cts-n-pa1 { /* DSR GPIO */
    609				nvidia,pins = "uart3_cts_n_pa1";
    610				nvidia,function = "gmi";
    611				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    612				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    613				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    614			};
    615			uart3-rts-n-pc0 { /* DTR GPIO */
    616				nvidia,pins = "uart3_rts_n_pc0";
    617				nvidia,function = "gmi";
    618				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    619				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    620				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    621			};
    622
    623			/* Apalis UART2 */
    624			uart2-txd-pc2 {
    625				nvidia,pins = "uart2_txd_pc2";
    626				nvidia,function = "irda";
    627				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    628				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    629				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    630			};
    631			uart2-rxd-pc3 {
    632				nvidia,pins = "uart2_rxd_pc3";
    633				nvidia,function = "irda";
    634				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    635				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    636				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    637			};
    638			uart2-cts-n-pj5 {
    639				nvidia,pins = "uart2_cts_n_pj5";
    640				nvidia,function = "uartb";
    641				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    642				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    643				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    644			};
    645			uart2-rts-n-pj6 {
    646				nvidia,pins = "uart2_rts_n_pj6";
    647				nvidia,function = "uartb";
    648				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    649				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    650				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    651			};
    652
    653			/* Apalis UART3 */
    654			uart3-txd-pw6 {
    655				nvidia,pins = "uart3_txd_pw6";
    656				nvidia,function = "uartc";
    657				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    658				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    659				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    660			};
    661			uart3-rxd-pw7 {
    662				nvidia,pins = "uart3_rxd_pw7";
    663				nvidia,function = "uartc";
    664				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    665				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    666				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    667			};
    668
    669			/* Apalis UART4 */
    670			uart4-rxd-pb0 {
    671				nvidia,pins = "pb0";
    672				nvidia,function = "uartd";
    673				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    674				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    675				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    676			};
    677			uart4-txd-pj7 {
    678				nvidia,pins = "pj7";
    679				nvidia,function = "uartd";
    680				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    681				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    682				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    683			};
    684
    685			/* Apalis USBH_EN */
    686			usb-vbus-en1-pn5 {
    687				nvidia,pins = "usb_vbus_en1_pn5";
    688				nvidia,function = "rsvd2";
    689				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    690				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    691				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    692				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
    693			};
    694
    695			/* Apalis USBH_OC# */
    696			pbb0 {
    697				nvidia,pins = "pbb0";
    698				nvidia,function = "vgp6";
    699				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    700				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    701				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    702			};
    703
    704			/* Apalis USBO1_EN */
    705			usb-vbus-en0-pn4 {
    706				nvidia,pins = "usb_vbus_en0_pn4";
    707				nvidia,function = "rsvd2";
    708				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    709				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    710				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    711				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
    712			};
    713
    714			/* Apalis USBO1_OC# */
    715			pbb4 {
    716				nvidia,pins = "pbb4";
    717				nvidia,function = "vgp4";
    718				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    719				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    720				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    721			};
    722
    723			/* Apalis WAKE1_MICO */
    724			pex-wake-n-pdd3 {
    725				nvidia,pins = "pex_wake_n_pdd3";
    726				nvidia,function = "rsvd2";
    727				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    728				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    729				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    730			};
    731
    732			/* CORE_PWR_REQ */
    733			core-pwr-req {
    734				nvidia,pins = "core_pwr_req";
    735				nvidia,function = "pwron";
    736				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    737				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    738				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    739			};
    740
    741			/* CPU_PWR_REQ */
    742			cpu-pwr-req {
    743				nvidia,pins = "cpu_pwr_req";
    744				nvidia,function = "cpu";
    745				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    746				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    747				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    748			};
    749
    750			/* DVFS */
    751			dvfs-pwm-px0 {
    752				nvidia,pins = "dvfs_pwm_px0";
    753				nvidia,function = "cldvfs";
    754				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    755				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    756				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    757			};
    758			dvfs-clk-px2 {
    759				nvidia,pins = "dvfs_clk_px2";
    760				nvidia,function = "cldvfs";
    761				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    762				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    763				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    764			};
    765
    766			/* eMMC */
    767			sdmmc4-dat0-paa0 {
    768				nvidia,pins = "sdmmc4_dat0_paa0";
    769				nvidia,function = "sdmmc4";
    770				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    771				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    772				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    773			};
    774			sdmmc4-dat1-paa1 {
    775				nvidia,pins = "sdmmc4_dat1_paa1";
    776				nvidia,function = "sdmmc4";
    777				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    778				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    779				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    780			};
    781			sdmmc4-dat2-paa2 {
    782				nvidia,pins = "sdmmc4_dat2_paa2";
    783				nvidia,function = "sdmmc4";
    784				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    785				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    786				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    787			};
    788			sdmmc4-dat3-paa3 {
    789				nvidia,pins = "sdmmc4_dat3_paa3";
    790				nvidia,function = "sdmmc4";
    791				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    792				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    793				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    794			};
    795			sdmmc4-dat4-paa4 {
    796				nvidia,pins = "sdmmc4_dat4_paa4";
    797				nvidia,function = "sdmmc4";
    798				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    799				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    800				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    801			};
    802			sdmmc4-dat5-paa5 {
    803				nvidia,pins = "sdmmc4_dat5_paa5";
    804				nvidia,function = "sdmmc4";
    805				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    806				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    807				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    808			};
    809			sdmmc4-dat6-paa6 {
    810				nvidia,pins = "sdmmc4_dat6_paa6";
    811				nvidia,function = "sdmmc4";
    812				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    813				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    814				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    815			};
    816			sdmmc4-dat7-paa7 {
    817				nvidia,pins = "sdmmc4_dat7_paa7";
    818				nvidia,function = "sdmmc4";
    819				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    820				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    821				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    822			};
    823			sdmmc4-clk-pcc4 {
    824				nvidia,pins = "sdmmc4_clk_pcc4";
    825				nvidia,function = "sdmmc4";
    826				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    827				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    828				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    829			};
    830			sdmmc4-cmd-pt7 {
    831				nvidia,pins = "sdmmc4_cmd_pt7";
    832				nvidia,function = "sdmmc4";
    833				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    834				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    835				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    836			};
    837
    838			/* JTAG_RTCK */
    839			jtag-rtck {
    840				nvidia,pins = "jtag_rtck";
    841				nvidia,function = "rtck";
    842				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    843				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    844				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    845			};
    846
    847			/* LAN_DEV_OFF# */
    848			ulpi-data5-po6 {
    849				nvidia,pins = "ulpi_data5_po6";
    850				nvidia,function = "ulpi";
    851				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    852				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    853				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    854			};
    855
    856			/* LAN_RESET# */
    857			kb-row10-ps2 {
    858				nvidia,pins = "kb_row10_ps2";
    859				nvidia,function = "rsvd2";
    860				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    861				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    862				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    863			};
    864
    865			/* LAN_WAKE# */
    866			ulpi-data4-po5 {
    867				nvidia,pins = "ulpi_data4_po5";
    868				nvidia,function = "ulpi";
    869				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    870				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    871				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    872			};
    873
    874			/* MCU_INT1# */
    875			pk2 {
    876				nvidia,pins = "pk2";
    877				nvidia,function = "rsvd1";
    878				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    879				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    880				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    881			};
    882
    883			/* MCU_INT2# */
    884			pj2 {
    885				nvidia,pins = "pj2";
    886				nvidia,function = "rsvd1";
    887				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    888				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    889				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    890			};
    891
    892			/* MCU_INT3# */
    893			pi5 {
    894				nvidia,pins = "pi5";
    895				nvidia,function = "rsvd2";
    896				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    897				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    898				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    899			};
    900
    901			/* MCU_INT4# */
    902			pj0 {
    903				nvidia,pins = "pj0";
    904				nvidia,function = "rsvd1";
    905				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    906				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    907				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    908			};
    909
    910			/* MCU_RESET */
    911			pbb6 {
    912				nvidia,pins = "pbb6";
    913				nvidia,function = "rsvd2";
    914				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    915				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    916				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    917			};
    918
    919			/* MCU SPI */
    920			gpio-x4-aud-px4 {
    921				nvidia,pins = "gpio_x4_aud_px4";
    922				nvidia,function = "spi2";
    923				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    924				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    925				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    926			};
    927			gpio-x5-aud-px5 {
    928				nvidia,pins = "gpio_x5_aud_px5";
    929				nvidia,function = "spi2";
    930				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    931				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    932				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    933			};
    934			gpio-x6-aud-px6 { /* MCU_CS */
    935				nvidia,pins = "gpio_x6_aud_px6";
    936				nvidia,function = "spi2";
    937				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    938				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    939				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    940			};
    941			gpio-x7-aud-px7 {
    942				nvidia,pins = "gpio_x7_aud_px7";
    943				nvidia,function = "spi2";
    944				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    945				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    946				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    947			};
    948			gpio-w2-aud-pw2 { /* MCU_CSEZP */
    949				nvidia,pins = "gpio_w2_aud_pw2";
    950				nvidia,function = "spi2";
    951				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    952				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    953				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    954			};
    955
    956			/* PMIC_CLK_32K */
    957			clk-32k-in {
    958				nvidia,pins = "clk_32k_in";
    959				nvidia,function = "clk";
    960				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    961				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    962				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    963			};
    964
    965			/* PMIC_CPU_OC_INT */
    966			clk-32k-out-pa0 {
    967				nvidia,pins = "clk_32k_out_pa0";
    968				nvidia,function = "soc";
    969				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    970				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    971				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    972			};
    973
    974			/* PWR_I2C */
    975			pwr-i2c-scl-pz6 {
    976				nvidia,pins = "pwr_i2c_scl_pz6";
    977				nvidia,function = "i2cpwr";
    978				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    979				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    980				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    981				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
    982			};
    983			pwr-i2c-sda-pz7 {
    984				nvidia,pins = "pwr_i2c_sda_pz7";
    985				nvidia,function = "i2cpwr";
    986				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    987				nvidia,tristate = <TEGRA_PIN_DISABLE>;
    988				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    989				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
    990			};
    991
    992			/* PWR_INT_N */
    993			pwr-int-n {
    994				nvidia,pins = "pwr_int_n";
    995				nvidia,function = "pmi";
    996				nvidia,pull = <TEGRA_PIN_PULL_UP>;
    997				nvidia,tristate = <TEGRA_PIN_ENABLE>;
    998				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    999			};
   1000
   1001			/* RESET_MOCI_CTRL */
   1002			pu4 {
   1003				nvidia,pins = "pu4";
   1004				nvidia,function = "gmi";
   1005				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
   1006				nvidia,tristate = <TEGRA_PIN_DISABLE>;
   1007				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1008			};
   1009
   1010			/* RESET_OUT_N */
   1011			reset-out-n {
   1012				nvidia,pins = "reset_out_n";
   1013				nvidia,function = "reset_out_n";
   1014				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
   1015				nvidia,tristate = <TEGRA_PIN_DISABLE>;
   1016				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
   1017			};
   1018
   1019			/* SHIFT_CTRL_DIR_IN */
   1020			kb-row0-pr0 {
   1021				nvidia,pins = "kb_row0_pr0";
   1022				nvidia,function = "rsvd2";
   1023				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1024				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1025				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1026			};
   1027			kb-row1-pr1 {
   1028				nvidia,pins = "kb_row1_pr1";
   1029				nvidia,function = "rsvd2";
   1030				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1031				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1032				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1033			};
   1034
   1035			/* Configure level-shifter as output for HDA */
   1036			kb-row11-ps3 {
   1037				nvidia,pins = "kb_row11_ps3";
   1038				nvidia,function = "rsvd2";
   1039				nvidia,pull = <TEGRA_PIN_PULL_UP>;
   1040				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1041				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1042			};
   1043
   1044			/* SHIFT_CTRL_DIR_OUT */
   1045			kb-col5-pq5 {
   1046				nvidia,pins = "kb_col5_pq5";
   1047				nvidia,function = "rsvd2";
   1048				nvidia,pull = <TEGRA_PIN_PULL_UP>;
   1049				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1050				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1051			};
   1052			kb-col6-pq6 {
   1053				nvidia,pins = "kb_col6_pq6";
   1054				nvidia,function = "rsvd2";
   1055				nvidia,pull = <TEGRA_PIN_PULL_UP>;
   1056				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1057				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1058			};
   1059			kb-col7-pq7 {
   1060				nvidia,pins = "kb_col7_pq7";
   1061				nvidia,function = "rsvd2";
   1062				nvidia,pull = <TEGRA_PIN_PULL_UP>;
   1063				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1064				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1065			};
   1066
   1067			/* SHIFT_CTRL_OE */
   1068			kb-col0-pq0 {
   1069				nvidia,pins = "kb_col0_pq0";
   1070				nvidia,function = "rsvd2";
   1071				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1072				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1073				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1074			};
   1075			kb-col1-pq1 {
   1076				nvidia,pins = "kb_col1_pq1";
   1077				nvidia,function = "rsvd2";
   1078				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1079				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1080				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1081			};
   1082			kb-col2-pq2 {
   1083				nvidia,pins = "kb_col2_pq2";
   1084				nvidia,function = "rsvd2";
   1085				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1086				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1087				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1088			};
   1089			kb-col4-pq4 {
   1090				nvidia,pins = "kb_col4_pq4";
   1091				nvidia,function = "kbc";
   1092				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1093				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1094				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1095			};
   1096			kb-row2-pr2 {
   1097				nvidia,pins = "kb_row2_pr2";
   1098				nvidia,function = "rsvd2";
   1099				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1100				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1101				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1102			};
   1103
   1104			/* GPIO_PI6 aka TMP451 ALERT#/THERM2# */
   1105			pi6 {
   1106				nvidia,pins = "pi6";
   1107				nvidia,function = "rsvd1";
   1108				nvidia,pull = <TEGRA_PIN_PULL_UP>;
   1109				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1110				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
   1111			};
   1112
   1113			/* TOUCH_INT */
   1114			gpio-w3-aud-pw3 {
   1115				nvidia,pins = "gpio_w3_aud_pw3";
   1116				nvidia,function = "spi6";
   1117				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
   1118				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1119				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
   1120			};
   1121
   1122			pc7 { /* NC */
   1123				nvidia,pins = "pc7";
   1124				nvidia,function = "rsvd1";
   1125				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1126				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1127				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1128			};
   1129			pg0 { /* NC */
   1130				nvidia,pins = "pg0";
   1131				nvidia,function = "rsvd1";
   1132				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1133				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1134				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1135			};
   1136			pg1 { /* NC */
   1137				nvidia,pins = "pg1";
   1138				nvidia,function = "rsvd1";
   1139				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1140				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1141				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1142			};
   1143			pg2 { /* NC */
   1144				nvidia,pins = "pg2";
   1145				nvidia,function = "rsvd1";
   1146				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1147				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1148				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1149			};
   1150			pg3 { /* NC */
   1151				nvidia,pins = "pg3";
   1152				nvidia,function = "rsvd1";
   1153				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1154				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1155				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1156			};
   1157			pg4 { /* NC */
   1158				nvidia,pins = "pg4";
   1159				nvidia,function = "rsvd1";
   1160				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1161				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1162				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1163			};
   1164			ph4 { /* NC */
   1165				nvidia,pins = "ph4";
   1166				nvidia,function = "rsvd2";
   1167				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1168				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1169				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1170			};
   1171			ph5 { /* NC */
   1172				nvidia,pins = "ph5";
   1173				nvidia,function = "rsvd2";
   1174				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1175				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1176				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1177			};
   1178			ph6 { /* NC */
   1179				nvidia,pins = "ph6";
   1180				nvidia,function = "gmi";
   1181				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1182				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1183				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1184			};
   1185			ph7 { /* NC */
   1186				nvidia,pins = "ph7";
   1187				nvidia,function = "gmi";
   1188				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1189				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1190				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1191			};
   1192			pi0 { /* NC */
   1193				nvidia,pins = "pi0";
   1194				nvidia,function = "rsvd1";
   1195				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1196				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1197				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1198			};
   1199			pi1 { /* NC */
   1200				nvidia,pins = "pi1";
   1201				nvidia,function = "rsvd1";
   1202				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1203				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1204				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1205			};
   1206			pi2 { /* NC */
   1207				nvidia,pins = "pi2";
   1208				nvidia,function = "rsvd4";
   1209				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1210				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1211				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1212			};
   1213			pi4 { /* NC */
   1214				nvidia,pins = "pi4";
   1215				nvidia,function = "gmi";
   1216				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1217				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1218				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1219			};
   1220			pi7 { /* NC */
   1221				nvidia,pins = "pi7";
   1222				nvidia,function = "rsvd1";
   1223				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1224				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1225				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1226			};
   1227			pk0 { /* NC */
   1228				nvidia,pins = "pk0";
   1229				nvidia,function = "rsvd1";
   1230				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1231				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1232				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1233			};
   1234			pk1 { /* NC */
   1235				nvidia,pins = "pk1";
   1236				nvidia,function = "rsvd4";
   1237				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1238				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1239				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1240			};
   1241			pk3 { /* NC */
   1242				nvidia,pins = "pk3";
   1243				nvidia,function = "gmi";
   1244				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1245				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1246				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1247			};
   1248			pk4 { /* NC */
   1249				nvidia,pins = "pk4";
   1250				nvidia,function = "rsvd2";
   1251				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1252				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1253				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1254			};
   1255			dap1-fs-pn0 { /* NC */
   1256				nvidia,pins = "dap1_fs_pn0";
   1257				nvidia,function = "rsvd4";
   1258				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1259				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1260				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1261			};
   1262			dap1-din-pn1 { /* NC */
   1263				nvidia,pins = "dap1_din_pn1";
   1264				nvidia,function = "rsvd4";
   1265				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1266				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1267				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1268			};
   1269			dap1-sclk-pn3 { /* NC */
   1270				nvidia,pins = "dap1_sclk_pn3";
   1271				nvidia,function = "rsvd4";
   1272				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1273				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1274				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1275			};
   1276			ulpi-data7-po0 { /* NC */
   1277				nvidia,pins = "ulpi_data7_po0";
   1278				nvidia,function = "ulpi";
   1279				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1280				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1281				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1282			};
   1283			ulpi-data0-po1 { /* NC */
   1284				nvidia,pins = "ulpi_data0_po1";
   1285				nvidia,function = "ulpi";
   1286				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1287				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1288				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1289			};
   1290			ulpi-data1-po2 { /* NC */
   1291				nvidia,pins = "ulpi_data1_po2";
   1292				nvidia,function = "ulpi";
   1293				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1294				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1295				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1296			};
   1297			ulpi-data2-po3 { /* NC */
   1298				nvidia,pins = "ulpi_data2_po3";
   1299				nvidia,function = "ulpi";
   1300				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1301				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1302				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1303			};
   1304			ulpi-data3-po4 { /* NC */
   1305				nvidia,pins = "ulpi_data3_po4";
   1306				nvidia,function = "ulpi";
   1307				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1308				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1309				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1310			};
   1311			ulpi-data6-po7 { /* NC */
   1312				nvidia,pins = "ulpi_data6_po7";
   1313				nvidia,function = "ulpi";
   1314				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1315				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1316				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1317			};
   1318			dap4-fs-pp4 { /* NC */
   1319				nvidia,pins = "dap4_fs_pp4";
   1320				nvidia,function = "rsvd4";
   1321				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1322				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1323				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1324			};
   1325			dap4-din-pp5 { /* NC */
   1326				nvidia,pins = "dap4_din_pp5";
   1327				nvidia,function = "rsvd3";
   1328				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1329				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1330				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1331			};
   1332			dap4-dout-pp6 { /* NC */
   1333				nvidia,pins = "dap4_dout_pp6";
   1334				nvidia,function = "rsvd4";
   1335				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1336				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1337				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1338			};
   1339			dap4-sclk-pp7 { /* NC */
   1340				nvidia,pins = "dap4_sclk_pp7";
   1341				nvidia,function = "rsvd3";
   1342				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1343				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1344				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1345			};
   1346			kb-col3-pq3 { /* NC */
   1347				nvidia,pins = "kb_col3_pq3";
   1348				nvidia,function = "kbc";
   1349				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1350				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1351				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1352			};
   1353			kb-row3-pr3 { /* NC */
   1354				nvidia,pins = "kb_row3_pr3";
   1355				nvidia,function = "kbc";
   1356				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1357				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1358				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1359			};
   1360			kb-row4-pr4 { /* NC */
   1361				nvidia,pins = "kb_row4_pr4";
   1362				nvidia,function = "rsvd3";
   1363				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1364				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1365				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1366			};
   1367			kb-row5-pr5 { /* NC */
   1368				nvidia,pins = "kb_row5_pr5";
   1369				nvidia,function = "rsvd3";
   1370				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1371				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1372				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1373			};
   1374			kb-row6-pr6 { /* NC */
   1375				nvidia,pins = "kb_row6_pr6";
   1376				nvidia,function = "kbc";
   1377				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1378				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1379				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1380			};
   1381			kb-row7-pr7 { /* NC */
   1382				nvidia,pins = "kb_row7_pr7";
   1383				nvidia,function = "rsvd2";
   1384				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1385				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1386				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1387			};
   1388			kb-row8-ps0 { /* NC */
   1389				nvidia,pins = "kb_row8_ps0";
   1390				nvidia,function = "rsvd2";
   1391				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1392				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1393				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1394			};
   1395			kb-row9-ps1 { /* NC */
   1396				nvidia,pins = "kb_row9_ps1";
   1397				nvidia,function = "rsvd2";
   1398				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1399				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1400				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1401			};
   1402			kb-row12-ps4 { /* NC */
   1403				nvidia,pins = "kb_row12_ps4";
   1404				nvidia,function = "rsvd2";
   1405				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1406				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1407				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1408			};
   1409			kb-row13-ps5 { /* NC */
   1410				nvidia,pins = "kb_row13_ps5";
   1411				nvidia,function = "rsvd2";
   1412				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1413				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1414				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1415			};
   1416			kb-row14-ps6 { /* NC */
   1417				nvidia,pins = "kb_row14_ps6";
   1418				nvidia,function = "rsvd2";
   1419				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1420				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1421				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1422			};
   1423			kb-row15-ps7 { /* NC */
   1424				nvidia,pins = "kb_row15_ps7";
   1425				nvidia,function = "rsvd3";
   1426				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1427				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1428				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1429			};
   1430			kb-row16-pt0 { /* NC */
   1431				nvidia,pins = "kb_row16_pt0";
   1432				nvidia,function = "rsvd2";
   1433				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1434				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1435				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1436			};
   1437			kb-row17-pt1 { /* NC */
   1438				nvidia,pins = "kb_row17_pt1";
   1439				nvidia,function = "rsvd2";
   1440				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1441				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1442				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1443			};
   1444			pu5 { /* NC */
   1445				nvidia,pins = "pu5";
   1446				nvidia,function = "gmi";
   1447				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1448				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1449				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1450			};
   1451			pv0 { /* NC */
   1452				nvidia,pins = "pv0";
   1453				nvidia,function = "rsvd1";
   1454				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1455				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1456				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1457			};
   1458			pv1 { /* NC */
   1459				nvidia,pins = "pv1";
   1460				nvidia,function = "rsvd1";
   1461				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1462				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1463				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1464			};
   1465			gpio-x1-aud-px1 { /* NC */
   1466				nvidia,pins = "gpio_x1_aud_px1";
   1467				nvidia,function = "rsvd2";
   1468				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1469				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1470				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1471			};
   1472			gpio-x3-aud-px3 { /* NC */
   1473				nvidia,pins = "gpio_x3_aud_px3";
   1474				nvidia,function = "rsvd4";
   1475				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1476				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1477				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1478			};
   1479			pbb7 { /* NC */
   1480				nvidia,pins = "pbb7";
   1481				nvidia,function = "rsvd2";
   1482				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1483				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1484				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1485			};
   1486			pcc1 { /* NC */
   1487				nvidia,pins = "pcc1";
   1488				nvidia,function = "rsvd2";
   1489				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1490				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1491				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1492			};
   1493			pcc2 { /* NC */
   1494				nvidia,pins = "pcc2";
   1495				nvidia,function = "rsvd2";
   1496				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1497				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1498				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1499			};
   1500			clk3-req-pee1 { /* NC */
   1501				nvidia,pins = "clk3_req_pee1";
   1502				nvidia,function = "rsvd2";
   1503				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1504				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1505				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1506			};
   1507			dap-mclk1-req-pee2 { /* NC */
   1508				nvidia,pins = "dap_mclk1_req_pee2";
   1509				nvidia,function = "rsvd4";
   1510				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
   1511				nvidia,tristate = <TEGRA_PIN_ENABLE>;
   1512				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   1513			};
   1514			/*
   1515			 * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
   1516			 * driver enabled aka not tristated and input driver
   1517			 * enabled as well as it features some magic properties
   1518			 * even though the external loopback is disabled and the
   1519			 * internal loopback used as per
   1520			 * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
   1521			 * bits being set to 0xfffd according to the TRM!
   1522			 */
   1523			sdmmc3-clk-lb-out-pee4 { /* NC */
   1524				nvidia,pins = "sdmmc3_clk_lb_out_pee4";
   1525				nvidia,function = "sdmmc3";
   1526				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
   1527				nvidia,tristate = <TEGRA_PIN_DISABLE>;
   1528				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
   1529			};
   1530		};
   1531	};
   1532
   1533	serial@70006040 {
   1534		compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
   1535		/delete-property/ reg-shift;
   1536	};
   1537
   1538	serial@70006200 {
   1539		compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
   1540		/delete-property/ reg-shift;
   1541	};
   1542
   1543	serial@70006300 {
   1544		compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
   1545		/delete-property/ reg-shift;
   1546	};
   1547
   1548	hdmi_ddc: i2c@7000c400 {
   1549		clock-frequency = <10000>;
   1550	};
   1551
   1552	/* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
   1553	i2c@7000d000 {
   1554		status = "okay";
   1555		clock-frequency = <400000>;
   1556
   1557		/* SGTL5000 audio codec */
   1558		sgtl5000: codec@a {
   1559			compatible = "fsl,sgtl5000";
   1560			reg = <0x0a>;
   1561			#sound-dai-cells = <0>;
   1562			VDDA-supply = <&reg_module_3v3_audio>;
   1563			VDDD-supply = <&reg_1v8_vddio>;
   1564			VDDIO-supply = <&reg_1v8_vddio>;
   1565			clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
   1566		};
   1567
   1568		pmic: pmic@40 {
   1569			compatible = "ams,as3722";
   1570			reg = <0x40>;
   1571			interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
   1572			ams,system-power-controller;
   1573			#interrupt-cells = <2>;
   1574			interrupt-controller;
   1575			gpio-controller;
   1576			#gpio-cells = <2>;
   1577			pinctrl-names = "default";
   1578			pinctrl-0 = <&as3722_default>;
   1579
   1580			as3722_default: pinmux {
   1581				gpio2-7 {
   1582					pins = "gpio2", /* PWR_EN_+V3.3 */
   1583					       "gpio7"; /* +V1.6_LPO */
   1584					function = "gpio";
   1585					bias-pull-up;
   1586				};
   1587
   1588				gpio0-1-3-4-5-6 {
   1589					pins = "gpio0", "gpio1", "gpio3",
   1590					       "gpio4", "gpio5", "gpio6";
   1591					bias-high-impedance;
   1592				};
   1593			};
   1594
   1595			regulators {
   1596				vsup-sd2-supply = <&reg_module_3v3>;
   1597				vsup-sd3-supply = <&reg_module_3v3>;
   1598				vsup-sd4-supply = <&reg_module_3v3>;
   1599				vsup-sd5-supply = <&reg_module_3v3>;
   1600				vin-ldo0-supply = <&reg_1v35_vddio_ddr>;
   1601				vin-ldo1-6-supply = <&reg_module_3v3>;
   1602				vin-ldo2-5-7-supply = <&reg_1v8_vddio>;
   1603				vin-ldo3-4-supply = <&reg_module_3v3>;
   1604				vin-ldo9-10-supply = <&reg_module_3v3>;
   1605				vin-ldo11-supply = <&reg_module_3v3>;
   1606
   1607				reg_vdd_cpu: sd0 {
   1608					regulator-name = "+VDD_CPU_AP";
   1609					regulator-min-microvolt = <700000>;
   1610					regulator-max-microvolt = <1400000>;
   1611					regulator-min-microamp = <3500000>;
   1612					regulator-max-microamp = <3500000>;
   1613					regulator-always-on;
   1614					regulator-boot-on;
   1615					ams,ext-control = <2>;
   1616				};
   1617
   1618				sd1 {
   1619					regulator-name = "+VDD_CORE";
   1620					regulator-min-microvolt = <700000>;
   1621					regulator-max-microvolt = <1350000>;
   1622					regulator-min-microamp = <2500000>;
   1623					regulator-max-microamp = <4000000>;
   1624					regulator-always-on;
   1625					regulator-boot-on;
   1626					ams,ext-control = <1>;
   1627				};
   1628
   1629				reg_1v35_vddio_ddr: sd2 {
   1630					regulator-name =
   1631						"+V1.35_VDDIO_DDR(sd2)";
   1632					regulator-min-microvolt = <1350000>;
   1633					regulator-max-microvolt = <1350000>;
   1634					regulator-always-on;
   1635					regulator-boot-on;
   1636				};
   1637
   1638				sd3 {
   1639					regulator-name =
   1640						"+V1.35_VDDIO_DDR(sd3)";
   1641					regulator-min-microvolt = <1350000>;
   1642					regulator-max-microvolt = <1350000>;
   1643					regulator-always-on;
   1644					regulator-boot-on;
   1645				};
   1646
   1647				reg_1v05_vdd: sd4 {
   1648					regulator-name = "+V1.05";
   1649					regulator-min-microvolt = <1050000>;
   1650					regulator-max-microvolt = <1050000>;
   1651				};
   1652
   1653				reg_1v8_vddio: sd5 {
   1654					regulator-name = "+V1.8";
   1655					regulator-min-microvolt = <1800000>;
   1656					regulator-max-microvolt = <1800000>;
   1657					regulator-boot-on;
   1658					regulator-always-on;
   1659				};
   1660
   1661				reg_vdd_gpu: sd6 {
   1662					regulator-name = "+VDD_GPU_AP";
   1663					regulator-min-microvolt = <650000>;
   1664					regulator-max-microvolt = <1200000>;
   1665					regulator-min-microamp = <3500000>;
   1666					regulator-max-microamp = <3500000>;
   1667					regulator-boot-on;
   1668					regulator-always-on;
   1669				};
   1670
   1671				reg_1v05_avdd: ldo0 {
   1672					regulator-name = "+V1.05_AVDD";
   1673					regulator-min-microvolt = <1050000>;
   1674					regulator-max-microvolt = <1050000>;
   1675					regulator-boot-on;
   1676					regulator-always-on;
   1677					ams,ext-control = <1>;
   1678				};
   1679
   1680				vddio_sdmmc1: ldo1 {
   1681					regulator-name = "VDDIO_SDMMC1";
   1682					regulator-min-microvolt = <1800000>;
   1683					regulator-max-microvolt = <3300000>;
   1684				};
   1685
   1686				ldo2 {
   1687					regulator-name = "+V1.2";
   1688					regulator-min-microvolt = <1200000>;
   1689					regulator-max-microvolt = <1200000>;
   1690					regulator-boot-on;
   1691					regulator-always-on;
   1692				};
   1693
   1694				ldo3 {
   1695					regulator-name = "+V1.05_RTC";
   1696					regulator-min-microvolt = <1000000>;
   1697					regulator-max-microvolt = <1000000>;
   1698					regulator-boot-on;
   1699					regulator-always-on;
   1700					ams,enable-tracking;
   1701				};
   1702
   1703				/* 1.8V for LVDS, 3.3V for eDP */
   1704				ldo4 {
   1705					regulator-name = "AVDD_LVDS0_PLL";
   1706					regulator-min-microvolt = <1800000>;
   1707					regulator-max-microvolt = <1800000>;
   1708				};
   1709
   1710				/* LDO5 not used */
   1711
   1712				vddio_sdmmc3: ldo6 {
   1713					regulator-name = "VDDIO_SDMMC3";
   1714					regulator-min-microvolt = <1800000>;
   1715					regulator-max-microvolt = <3300000>;
   1716				};
   1717
   1718				/* LDO7 not used */
   1719
   1720				ldo9 {
   1721					regulator-name = "+V3.3_ETH(ldo9)";
   1722					regulator-min-microvolt = <3300000>;
   1723					regulator-max-microvolt = <3300000>;
   1724					regulator-always-on;
   1725				};
   1726
   1727				ldo10 {
   1728					regulator-name = "+V3.3_ETH(ldo10)";
   1729					regulator-min-microvolt = <3300000>;
   1730					regulator-max-microvolt = <3300000>;
   1731					regulator-always-on;
   1732				};
   1733
   1734				ldo11 {
   1735					regulator-name = "+V1.8_VPP_FUSE";
   1736					regulator-min-microvolt = <1800000>;
   1737					regulator-max-microvolt = <1800000>;
   1738				};
   1739			};
   1740		};
   1741
   1742		/*
   1743		 * TMP451 temperature sensor
   1744		 * Note: THERM_N directly connected to AS3722 PMIC THERM
   1745		 */
   1746		temp-sensor@4c {
   1747			compatible = "ti,tmp451";
   1748			reg = <0x4c>;
   1749			interrupt-parent = <&gpio>;
   1750			interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_EDGE_FALLING>;
   1751			#thermal-sensor-cells = <1>;
   1752			vcc-supply = <&reg_module_3v3>;
   1753		};
   1754	};
   1755
   1756	/* SPI2: MCU SPI */
   1757	spi@7000d600 {
   1758		status = "okay";
   1759		spi-max-frequency = <25000000>;
   1760	};
   1761
   1762	pmc@7000e400 {
   1763		nvidia,invert-interrupt;
   1764		nvidia,suspend-mode = <1>;
   1765		nvidia,cpu-pwr-good-time = <500>;
   1766		nvidia,cpu-pwr-off-time = <300>;
   1767		nvidia,core-pwr-good-time = <641 3845>;
   1768		nvidia,core-pwr-off-time = <61036>;
   1769		nvidia,core-power-req-active-high;
   1770		nvidia,sys-clock-req-active-high;
   1771
   1772		/* Set power_off bit in ResetControl register of AS3722 PMIC */
   1773		i2c-thermtrip {
   1774			nvidia,i2c-controller-id = <4>;
   1775			nvidia,bus-addr = <0x40>;
   1776			nvidia,reg-addr = <0x36>;
   1777			nvidia,reg-data = <0x2>;
   1778		};
   1779	};
   1780
   1781	sata@70020000 {
   1782		phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
   1783		phy-names = "sata-0";
   1784		avdd-supply = <&reg_1v05_vdd>;
   1785		hvdd-supply = <&reg_module_3v3>;
   1786		vddio-supply = <&reg_1v05_vdd>;
   1787	};
   1788
   1789	usb@70090000 {
   1790		/* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */
   1791		phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
   1792		       <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
   1793		       <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
   1794		       <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
   1795		       <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
   1796		phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
   1797		avddio-pex-supply = <&reg_1v05_vdd>;
   1798		avdd-pll-erefe-supply = <&reg_1v05_avdd>;
   1799		avdd-pll-utmip-supply = <&reg_1v8_vddio>;
   1800		avdd-usb-ss-pll-supply = <&reg_1v05_vdd>;
   1801		avdd-usb-supply = <&reg_module_3v3>;
   1802		dvddio-pex-supply = <&reg_1v05_vdd>;
   1803		hvdd-usb-ss-pll-e-supply = <&reg_module_3v3>;
   1804		hvdd-usb-ss-supply = <&reg_module_3v3>;
   1805	};
   1806
   1807	padctl@7009f000 {
   1808		avdd-pll-utmip-supply = <&reg_1v8_vddio>;
   1809		avdd-pll-erefe-supply = <&reg_1v05_avdd>;
   1810		avdd-pex-pll-supply = <&reg_1v05_vdd>;
   1811		hvdd-pex-pll-e-supply = <&reg_module_3v3>;
   1812
   1813		pads {
   1814			usb2 {
   1815				status = "okay";
   1816
   1817				lanes {
   1818					usb2-0 {
   1819						status = "okay";
   1820						nvidia,function = "xusb";
   1821					};
   1822
   1823					usb2-1 {
   1824						status = "okay";
   1825						nvidia,function = "xusb";
   1826					};
   1827
   1828					usb2-2 {
   1829						status = "okay";
   1830						nvidia,function = "xusb";
   1831					};
   1832				};
   1833			};
   1834
   1835			pcie {
   1836				status = "okay";
   1837
   1838				lanes {
   1839					pcie-0 {
   1840						status = "okay";
   1841						nvidia,function = "usb3-ss";
   1842					};
   1843
   1844					pcie-1 {
   1845						status = "okay";
   1846						nvidia,function = "usb3-ss";
   1847					};
   1848
   1849					pcie-2 {
   1850						status = "okay";
   1851						nvidia,function = "pcie";
   1852					};
   1853
   1854					pcie-3 {
   1855						status = "okay";
   1856						nvidia,function = "pcie";
   1857					};
   1858
   1859					pcie-4 {
   1860						status = "okay";
   1861						nvidia,function = "pcie";
   1862					};
   1863				};
   1864			};
   1865
   1866			sata {
   1867				status = "okay";
   1868
   1869				lanes {
   1870					sata-0 {
   1871						status = "okay";
   1872						nvidia,function = "sata";
   1873					};
   1874				};
   1875			};
   1876		};
   1877
   1878		ports {
   1879			/* USBO1 */
   1880			usb2-0 {
   1881				status = "okay";
   1882				mode = "otg";
   1883				usb-role-switch;
   1884				vbus-supply = <&reg_usbo1_vbus>;
   1885			};
   1886
   1887			/* USBH2 */
   1888			usb2-1 {
   1889				status = "okay";
   1890				mode = "host";
   1891				vbus-supply = <&reg_usbh_vbus>;
   1892			};
   1893
   1894			/* USBH4 */
   1895			usb2-2 {
   1896				status = "okay";
   1897				mode = "host";
   1898				vbus-supply = <&reg_usbh_vbus>;
   1899			};
   1900
   1901			usb3-0 {
   1902				status = "okay";
   1903				nvidia,usb2-companion = <2>;
   1904				vbus-supply = <&reg_usbh_vbus>;
   1905			};
   1906
   1907			usb3-1 {
   1908				status = "okay";
   1909				nvidia,usb2-companion = <0>;
   1910				vbus-supply = <&reg_usbo1_vbus>;
   1911			};
   1912		};
   1913	};
   1914
   1915	/* eMMC */
   1916	mmc@700b0600 {
   1917		status = "okay";
   1918		bus-width = <8>;
   1919		non-removable;
   1920		vmmc-supply = <&reg_module_3v3>; /* VCC */
   1921		vqmmc-supply = <&reg_1v8_vddio>; /* VCCQ */
   1922		mmc-ddr-1_8v;
   1923	};
   1924
   1925	/* CPU DFLL clock */
   1926	clock@70110000 {
   1927		status = "okay";
   1928		nvidia,i2c-fs-rate = <400000>;
   1929		vdd-cpu-supply = <&reg_vdd_cpu>;
   1930	};
   1931
   1932	ahub@70300000 {
   1933		i2s@70301200 {
   1934			status = "okay";
   1935		};
   1936	};
   1937
   1938	clk32k_in: osc3 {
   1939		compatible = "fixed-clock";
   1940		#clock-cells = <0>;
   1941		clock-frequency = <32768>;
   1942	};
   1943
   1944	cpus {
   1945		cpu@0 {
   1946			vdd-cpu-supply = <&reg_vdd_cpu>;
   1947		};
   1948	};
   1949
   1950	reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
   1951		compatible = "regulator-fixed";
   1952		regulator-name = "+V1.05_AVDD_HDMI_PLL";
   1953		regulator-min-microvolt = <1050000>;
   1954		regulator-max-microvolt = <1050000>;
   1955		gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
   1956		vin-supply = <&reg_1v05_vdd>;
   1957	};
   1958
   1959	reg_3v3_mxm: regulator-3v3-mxm {
   1960		compatible = "regulator-fixed";
   1961		regulator-name = "+V3.3_MXM";
   1962		regulator-min-microvolt = <3300000>;
   1963		regulator-max-microvolt = <3300000>;
   1964		regulator-always-on;
   1965		regulator-boot-on;
   1966	};
   1967
   1968	reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
   1969		compatible = "regulator-fixed";
   1970		regulator-name = "+V3.3_AVDD_HDMI";
   1971		regulator-min-microvolt = <3300000>;
   1972		regulator-max-microvolt = <3300000>;
   1973		vin-supply = <&reg_1v05_vdd>;
   1974	};
   1975
   1976	reg_module_3v3: regulator-module-3v3 {
   1977		compatible = "regulator-fixed";
   1978		regulator-name = "+V3.3";
   1979		regulator-min-microvolt = <3300000>;
   1980		regulator-max-microvolt = <3300000>;
   1981		regulator-always-on;
   1982		regulator-boot-on;
   1983		/* PWR_EN_+V3.3 */
   1984		gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
   1985		enable-active-high;
   1986		vin-supply = <&reg_3v3_mxm>;
   1987	};
   1988
   1989	reg_module_3v3_audio: regulator-module-3v3-audio {
   1990		compatible = "regulator-fixed";
   1991		regulator-name = "+V3.3_AUDIO_AVDD_S";
   1992		regulator-min-microvolt = <3300000>;
   1993		regulator-max-microvolt = <3300000>;
   1994		regulator-always-on;
   1995	};
   1996
   1997	sound {
   1998		compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1",
   1999			     "nvidia,tegra-audio-sgtl5000";
   2000		nvidia,model = "Toradex Apalis TK1";
   2001		nvidia,audio-routing =
   2002			"Headphone Jack", "HP_OUT",
   2003			"LINE_IN", "Line In Jack",
   2004			"MIC_IN", "Mic Jack";
   2005		nvidia,i2s-controller = <&tegra_i2s2>;
   2006		nvidia,audio-codec = <&sgtl5000>;
   2007		clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
   2008			 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
   2009			 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
   2010		clock-names = "pll_a", "pll_a_out0", "mclk";
   2011
   2012		assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
   2013				  <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
   2014
   2015		assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
   2016					 <&tegra_car TEGRA124_CLK_EXTERN1>;
   2017	};
   2018
   2019	thermal-zones {
   2020		cpu-thermal {
   2021			trips {
   2022				cpu-shutdown-trip {
   2023					temperature = <101000>;
   2024					hysteresis = <0>;
   2025					type = "critical";
   2026				};
   2027			};
   2028		};
   2029
   2030		mem-thermal {
   2031			trips {
   2032				mem-shutdown-trip {
   2033					temperature = <101000>;
   2034					hysteresis = <0>;
   2035					type = "critical";
   2036				};
   2037			};
   2038		};
   2039
   2040		gpu-thermal {
   2041			trips {
   2042				gpu-shutdown-trip {
   2043					temperature = <101000>;
   2044					hysteresis = <0>;
   2045					type = "critical";
   2046				};
   2047			};
   2048		};
   2049	};
   2050};
   2051
   2052&gpio {
   2053	/* I210 Gigabit Ethernet Controller Reset */
   2054	lan-reset-n-hog {
   2055		gpio-hog;
   2056		gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
   2057		output-high;
   2058		line-name = "LAN_RESET_N";
   2059	};
   2060
   2061	/* Control MXM3 pin 26 Reset Module Output Carrier Input */
   2062	reset-moci-ctrl-hog {
   2063		gpio-hog;
   2064		gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
   2065		output-high;
   2066		line-name = "RESET_MOCI_CTRL";
   2067	};
   2068};