cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

tegra20-tec.dts (2332B)

      1// SPDX-License-Identifier: GPL-2.0
      2/dts-v1/;
      3
      4#include "tegra20-tamonten.dtsi"
      5
      6/ {
      7	model = "Avionic Design Tamonten Evaluation Carrier";
      8	compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
      9
     10	host1x@50000000 {
     11		hdmi@54280000 {
     12			status = "okay";
     13		};
     14	};
     15
     16	i2c@7000c000 {
     17		wm8903: wm8903@1a {
     18			compatible = "wlf,wm8903";
     19			reg = <0x1a>;
     20			interrupt-parent = <&gpio>;
     21			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
     22
     23			gpio-controller;
     24			#gpio-cells = <2>;
     25
     26			micdet-cfg = <0>;
     27			micdet-delay = <100>;
     28			gpio-cfg = <0xffffffff
     29				    0xffffffff
     30				    0
     31				    0xffffffff
     32				    0xffffffff>;
     33		};
     34	};
     35
     36	pcie@80003000 {
     37		status = "okay";
     38
     39		pci@1,0 {
     40			status = "okay";
     41		};
     42	};
     43
     44	sound {
     45		compatible = "ad,tegra-audio-wm8903-tec",
     46			     "nvidia,tegra-audio-wm8903";
     47		nvidia,model = "Avionic Design TEC";
     48
     49		nvidia,audio-routing =
     50			"Headphone Jack", "HPOUTR",
     51			"Headphone Jack", "HPOUTL",
     52			"Int Spk", "ROP",
     53			"Int Spk", "RON",
     54			"Int Spk", "LOP",
     55			"Int Spk", "LON",
     56			"Mic Jack", "MICBIAS",
     57			"IN1L", "Mic Jack";
     58
     59		nvidia,i2s-controller = <&tegra_i2s1>;
     60		nvidia,audio-codec = <&wm8903>;
     61
     62		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
     63		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
     64			GPIO_ACTIVE_LOW>;
     65
     66		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
     67			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
     68			 <&tegra_car TEGRA20_CLK_CDEV1>;
     69		clock-names = "pll_a", "pll_a_out0", "mclk";
     70	};
     71
     72	vcc_24v_reg: regulator-24v {
     73		compatible = "regulator-fixed";
     74		regulator-name = "vcc_24v";
     75		regulator-min-microvolt = <24000000>;
     76		regulator-max-microvolt = <24000000>;
     77		regulator-always-on;
     78	};
     79
     80	vdd_5v0_reg: regulator-5v0 {
     81		compatible = "regulator-fixed";
     82		regulator-name = "vdd_5v0";
     83		vin-supply = <&vcc_24v_reg>;
     84		regulator-min-microvolt = <5000000>;
     85		regulator-max-microvolt = <5000000>;
     86		regulator-always-on;
     87	};
     88
     89	vdd_3v3_reg: regulator-3v3 {
     90		compatible = "regulator-fixed";
     91		regulator-name = "vdd_3v3";
     92		vin-supply = <&vcc_24v_reg>;
     93		regulator-min-microvolt = <3300000>;
     94		regulator-max-microvolt = <3300000>;
     95		regulator-always-on;
     96	};
     97
     98	vdd_1v8_reg: regulator-1v8 {
     99		compatible = "regulator-fixed";
    100		regulator-name = "vdd_1v8";
    101		vin-supply = <&vdd_3v3_reg>;
    102		regulator-min-microvolt = <1800000>;
    103		regulator-max-microvolt = <1800000>;
    104		regulator-always-on;
    105	};
    106};