uniphier-ld4.dtsi (10165B)
1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier LD4 SoC 4// 5// Copyright (C) 2015-2016 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/uniphier-gpio.h> 9 10/ { 11 compatible = "socionext,uniphier-ld4"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a9"; 22 reg = <0>; 23 enable-method = "psci"; 24 next-level-cache = <&l2>; 25 }; 26 }; 27 28 psci { 29 compatible = "arm,psci-0.2"; 30 method = "smc"; 31 }; 32 33 clocks { 34 refclk: ref { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <24576000>; 38 }; 39 40 arm_timer_clk: arm-timer { 41 #clock-cells = <0>; 42 compatible = "fixed-clock"; 43 clock-frequency = <50000000>; 44 }; 45 }; 46 47 soc { 48 compatible = "simple-bus"; 49 #address-cells = <1>; 50 #size-cells = <1>; 51 ranges; 52 interrupt-parent = <&intc>; 53 54 l2: cache-controller@500c0000 { 55 compatible = "socionext,uniphier-system-cache"; 56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, 57 <0x506c0000 0x400>; 58 interrupts = <0 174 4>, <0 175 4>; 59 cache-unified; 60 cache-size = <(512 * 1024)>; 61 cache-sets = <256>; 62 cache-line-size = <128>; 63 cache-level = <2>; 64 }; 65 66 spi: spi@54006000 { 67 compatible = "socionext,uniphier-scssi"; 68 status = "disabled"; 69 reg = <0x54006000 0x100>; 70 #address-cells = <1>; 71 #size-cells = <0>; 72 interrupts = <0 39 4>; 73 pinctrl-names = "default"; 74 pinctrl-0 = <&pinctrl_spi0>; 75 clocks = <&peri_clk 11>; 76 resets = <&peri_rst 11>; 77 }; 78 79 serial0: serial@54006800 { 80 compatible = "socionext,uniphier-uart"; 81 status = "disabled"; 82 reg = <0x54006800 0x40>; 83 interrupts = <0 33 4>; 84 pinctrl-names = "default"; 85 pinctrl-0 = <&pinctrl_uart0>; 86 clocks = <&peri_clk 0>; 87 resets = <&peri_rst 0>; 88 }; 89 90 serial1: serial@54006900 { 91 compatible = "socionext,uniphier-uart"; 92 status = "disabled"; 93 reg = <0x54006900 0x40>; 94 interrupts = <0 35 4>; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_uart1>; 97 clocks = <&peri_clk 1>; 98 resets = <&peri_rst 1>; 99 }; 100 101 serial2: serial@54006a00 { 102 compatible = "socionext,uniphier-uart"; 103 status = "disabled"; 104 reg = <0x54006a00 0x40>; 105 interrupts = <0 37 4>; 106 pinctrl-names = "default"; 107 pinctrl-0 = <&pinctrl_uart2>; 108 clocks = <&peri_clk 2>; 109 resets = <&peri_rst 2>; 110 }; 111 112 serial3: serial@54006b00 { 113 compatible = "socionext,uniphier-uart"; 114 status = "disabled"; 115 reg = <0x54006b00 0x40>; 116 interrupts = <0 29 4>; 117 pinctrl-names = "default"; 118 pinctrl-0 = <&pinctrl_uart3>; 119 clocks = <&peri_clk 3>; 120 resets = <&peri_rst 3>; 121 }; 122 123 gpio: gpio@55000000 { 124 compatible = "socionext,uniphier-gpio"; 125 reg = <0x55000000 0x200>; 126 interrupt-parent = <&aidet>; 127 interrupt-controller; 128 #interrupt-cells = <2>; 129 gpio-controller; 130 #gpio-cells = <2>; 131 gpio-ranges = <&pinctrl 0 0 0>; 132 gpio-ranges-group-names = "gpio_range"; 133 ngpios = <136>; 134 socionext,interrupt-ranges = <0 48 13>, <14 62 2>; 135 }; 136 137 i2c0: i2c@58400000 { 138 compatible = "socionext,uniphier-i2c"; 139 status = "disabled"; 140 reg = <0x58400000 0x40>; 141 #address-cells = <1>; 142 #size-cells = <0>; 143 interrupts = <0 41 1>; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pinctrl_i2c0>; 146 clocks = <&peri_clk 4>; 147 resets = <&peri_rst 4>; 148 clock-frequency = <100000>; 149 }; 150 151 i2c1: i2c@58480000 { 152 compatible = "socionext,uniphier-i2c"; 153 status = "disabled"; 154 reg = <0x58480000 0x40>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 interrupts = <0 42 1>; 158 pinctrl-names = "default"; 159 pinctrl-0 = <&pinctrl_i2c1>; 160 clocks = <&peri_clk 5>; 161 resets = <&peri_rst 5>; 162 clock-frequency = <100000>; 163 }; 164 165 /* chip-internal connection for DMD */ 166 i2c2: i2c@58500000 { 167 compatible = "socionext,uniphier-i2c"; 168 reg = <0x58500000 0x40>; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 interrupts = <0 43 1>; 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pinctrl_i2c2>; 174 clocks = <&peri_clk 6>; 175 resets = <&peri_rst 6>; 176 clock-frequency = <400000>; 177 }; 178 179 i2c3: i2c@58580000 { 180 compatible = "socionext,uniphier-i2c"; 181 status = "disabled"; 182 reg = <0x58580000 0x40>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 interrupts = <0 44 1>; 186 pinctrl-names = "default"; 187 pinctrl-0 = <&pinctrl_i2c3>; 188 clocks = <&peri_clk 7>; 189 resets = <&peri_rst 7>; 190 clock-frequency = <100000>; 191 }; 192 193 system_bus: system-bus@58c00000 { 194 compatible = "socionext,uniphier-system-bus"; 195 status = "disabled"; 196 reg = <0x58c00000 0x400>; 197 #address-cells = <2>; 198 #size-cells = <1>; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pinctrl_system_bus>; 201 }; 202 203 smpctrl@59801000 { 204 compatible = "socionext,uniphier-smpctrl"; 205 reg = <0x59801000 0x400>; 206 }; 207 208 mioctrl@59810000 { 209 compatible = "socionext,uniphier-ld4-mioctrl", 210 "simple-mfd", "syscon"; 211 reg = <0x59810000 0x800>; 212 213 mio_clk: clock { 214 compatible = "socionext,uniphier-ld4-mio-clock"; 215 #clock-cells = <1>; 216 }; 217 218 mio_rst: reset { 219 compatible = "socionext,uniphier-ld4-mio-reset"; 220 #reset-cells = <1>; 221 }; 222 }; 223 224 perictrl@59820000 { 225 compatible = "socionext,uniphier-ld4-perictrl", 226 "simple-mfd", "syscon"; 227 reg = <0x59820000 0x200>; 228 229 peri_clk: clock { 230 compatible = "socionext,uniphier-ld4-peri-clock"; 231 #clock-cells = <1>; 232 }; 233 234 peri_rst: reset { 235 compatible = "socionext,uniphier-ld4-peri-reset"; 236 #reset-cells = <1>; 237 }; 238 }; 239 240 dmac: dma-controller@5a000000 { 241 compatible = "socionext,uniphier-mio-dmac"; 242 reg = <0x5a000000 0x1000>; 243 interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, 244 <0 71 4>, <0 72 4>, <0 73 4>; 245 clocks = <&mio_clk 7>; 246 resets = <&mio_rst 7>; 247 #dma-cells = <1>; 248 }; 249 250 sd: mmc@5a400000 { 251 compatible = "socionext,uniphier-sd-v2.91"; 252 status = "disabled"; 253 reg = <0x5a400000 0x200>; 254 interrupts = <0 76 4>; 255 pinctrl-names = "default", "uhs"; 256 pinctrl-0 = <&pinctrl_sd>; 257 pinctrl-1 = <&pinctrl_sd_uhs>; 258 clocks = <&mio_clk 0>; 259 reset-names = "host", "bridge"; 260 resets = <&mio_rst 0>, <&mio_rst 3>; 261 dma-names = "rx-tx"; 262 dmas = <&dmac 4>; 263 bus-width = <4>; 264 cap-sd-highspeed; 265 sd-uhs-sdr12; 266 sd-uhs-sdr25; 267 sd-uhs-sdr50; 268 }; 269 270 emmc: mmc@5a500000 { 271 compatible = "socionext,uniphier-sd-v2.91"; 272 status = "disabled"; 273 reg = <0x5a500000 0x200>; 274 interrupts = <0 78 4>; 275 pinctrl-names = "default"; 276 pinctrl-0 = <&pinctrl_emmc>; 277 clocks = <&mio_clk 1>; 278 reset-names = "host", "bridge", "hw"; 279 resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; 280 dma-names = "rx-tx"; 281 dmas = <&dmac 6>; 282 bus-width = <8>; 283 cap-mmc-highspeed; 284 cap-mmc-hw-reset; 285 non-removable; 286 }; 287 288 usb0: usb@5a800100 { 289 compatible = "socionext,uniphier-ehci", "generic-ehci"; 290 status = "disabled"; 291 reg = <0x5a800100 0x100>; 292 interrupts = <0 80 4>; 293 pinctrl-names = "default"; 294 pinctrl-0 = <&pinctrl_usb0>; 295 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, 296 <&mio_clk 12>; 297 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 298 <&mio_rst 12>; 299 has-transaction-translator; 300 }; 301 302 usb1: usb@5a810100 { 303 compatible = "socionext,uniphier-ehci", "generic-ehci"; 304 status = "disabled"; 305 reg = <0x5a810100 0x100>; 306 interrupts = <0 81 4>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&pinctrl_usb1>; 309 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, 310 <&mio_clk 13>; 311 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 312 <&mio_rst 13>; 313 has-transaction-translator; 314 }; 315 316 usb2: usb@5a820100 { 317 compatible = "socionext,uniphier-ehci", "generic-ehci"; 318 status = "disabled"; 319 reg = <0x5a820100 0x100>; 320 interrupts = <0 82 4>; 321 pinctrl-names = "default"; 322 pinctrl-0 = <&pinctrl_usb2>; 323 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, 324 <&mio_clk 14>; 325 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 326 <&mio_rst 14>; 327 has-transaction-translator; 328 }; 329 330 soc-glue@5f800000 { 331 compatible = "socionext,uniphier-ld4-soc-glue", 332 "simple-mfd", "syscon"; 333 reg = <0x5f800000 0x2000>; 334 335 pinctrl: pinctrl { 336 compatible = "socionext,uniphier-ld4-pinctrl"; 337 }; 338 }; 339 340 soc-glue@5f900000 { 341 compatible = "socionext,uniphier-ld4-soc-glue-debug", 342 "simple-mfd"; 343 #address-cells = <1>; 344 #size-cells = <1>; 345 ranges = <0 0x5f900000 0x2000>; 346 347 efuse@100 { 348 compatible = "socionext,uniphier-efuse"; 349 reg = <0x100 0x28>; 350 }; 351 352 efuse@130 { 353 compatible = "socionext,uniphier-efuse"; 354 reg = <0x130 0x8>; 355 }; 356 }; 357 358 timer@60000200 { 359 compatible = "arm,cortex-a9-global-timer"; 360 reg = <0x60000200 0x20>; 361 interrupts = <1 11 0x104>; 362 clocks = <&arm_timer_clk>; 363 }; 364 365 timer@60000600 { 366 compatible = "arm,cortex-a9-twd-timer"; 367 reg = <0x60000600 0x20>; 368 interrupts = <1 13 0x104>; 369 clocks = <&arm_timer_clk>; 370 }; 371 372 intc: interrupt-controller@60001000 { 373 compatible = "arm,cortex-a9-gic"; 374 reg = <0x60001000 0x1000>, 375 <0x60000100 0x100>; 376 #interrupt-cells = <3>; 377 interrupt-controller; 378 }; 379 380 aidet: interrupt-controller@61830000 { 381 compatible = "socionext,uniphier-ld4-aidet"; 382 reg = <0x61830000 0x200>; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 }; 386 387 sysctrl@61840000 { 388 compatible = "socionext,uniphier-ld4-sysctrl", 389 "simple-mfd", "syscon"; 390 reg = <0x61840000 0x10000>; 391 392 sys_clk: clock { 393 compatible = "socionext,uniphier-ld4-clock"; 394 #clock-cells = <1>; 395 }; 396 397 sys_rst: reset { 398 compatible = "socionext,uniphier-ld4-reset"; 399 #reset-cells = <1>; 400 }; 401 }; 402 403 nand: nand-controller@68000000 { 404 compatible = "socionext,uniphier-denali-nand-v5a"; 405 status = "disabled"; 406 reg-names = "nand_data", "denali_reg"; 407 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 interrupts = <0 65 4>; 411 pinctrl-names = "default"; 412 pinctrl-0 = <&pinctrl_nand>; 413 clock-names = "nand", "nand_x", "ecc"; 414 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 415 reset-names = "nand", "reg"; 416 resets = <&sys_rst 2>, <&sys_rst 2>; 417 }; 418 }; 419}; 420 421#include "uniphier-pinctrl.dtsi"