cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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uniphier-ld6b-ref.dts (1356B)

      1// SPDX-License-Identifier: GPL-2.0+ OR MIT
      2//
      3// Device Tree Source for UniPhier LD6b Reference Board
      4//
      5// Copyright (C) 2015-2016 Socionext Inc.
      6//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
      7
      8/dts-v1/;
      9#include "uniphier-ld6b.dtsi"
     10#include "uniphier-ref-daughter.dtsi"
     11#include "uniphier-support-card.dtsi"
     12
     13/ {
     14	model = "UniPhier LD6b Reference Board";
     15	compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b";
     16
     17	chosen {
     18		stdout-path = "serial0:115200n8";
     19	};
     20
     21	aliases {
     22		serial0 = &serial0;
     23		serial1 = &serial1;
     24		serial2 = &serial2;
     25		serial3 = &serialsc;
     26		i2c0 = &i2c0;
     27		i2c1 = &i2c1;
     28		i2c2 = &i2c2;
     29		i2c3 = &i2c3;
     30		i2c4 = &i2c4;
     31		i2c5 = &i2c5;
     32		i2c6 = &i2c6;
     33		ethernet0 = &eth;
     34	};
     35
     36	memory@80000000 {
     37		device_type = "memory";
     38		reg = <0x80000000 0x80000000>;
     39	};
     40};
     41
     42&ethsc {
     43	interrupts = <4 8>;
     44};
     45
     46&serialsc {
     47	interrupts = <4 8>;
     48};
     49
     50&serial0 {
     51	status = "okay";
     52};
     53
     54&serial1 {
     55	status = "okay";
     56};
     57
     58&serial2 {
     59	status = "okay";
     60};
     61
     62&gpio {
     63	xirq4 {
     64		gpio-hog;
     65		gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
     66		input;
     67	};
     68};
     69
     70&i2c0 {
     71	status = "okay";
     72};
     73
     74&sd {
     75	status = "okay";
     76};
     77
     78&eth {
     79	status = "okay";
     80	phy-handle = <&ethphy>;
     81};
     82
     83&mdio {
     84	ethphy: ethernet-phy@0 {
     85		reg = <0>;
     86	};
     87};
     88
     89&usb0 {
     90	status = "okay";
     91};
     92
     93&usb1 {
     94	status = "okay";
     95};
     96
     97&nand {
     98	status = "okay";
     99
    100	nand@0 {
    101		reg = <0>;
    102	};
    103};