cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

uniphier-pro4-ace.dts (1258B)

      1// SPDX-License-Identifier: GPL-2.0+ OR MIT
      2//
      3// Device Tree Source for UniPhier Pro4 Ace Board
      4//
      5// Copyright (C) 2016 Socionext Inc.
      6//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
      7
      8/dts-v1/;
      9#include "uniphier-pro4.dtsi"
     10
     11/ {
     12	model = "UniPhier Pro4 Ace Board";
     13	compatible = "socionext,uniphier-pro4-ace", "socionext,uniphier-pro4";
     14
     15	chosen {
     16		stdout-path = "serial0:115200n8";
     17	};
     18
     19	aliases {
     20		serial0 = &serial0;
     21		serial1 = &serial1;
     22		serial2 = &serial2;
     23		i2c0 = &i2c0;
     24		i2c1 = &i2c1;
     25		i2c2 = &i2c2;
     26		i2c3 = &i2c3;
     27		i2c5 = &i2c5;
     28		i2c6 = &i2c6;
     29		ethernet0 = &eth;
     30	};
     31
     32	memory@80000000 {
     33		device_type = "memory";
     34		reg = <0x80000000 0x40000000>;
     35	};
     36};
     37
     38&serial0 {
     39	status = "okay";
     40};
     41
     42&serial1 {
     43	status = "okay";
     44};
     45
     46&serial2 {
     47	status = "okay";
     48};
     49
     50&i2c0 {
     51	status = "okay";
     52
     53	eeprom@54 {
     54		compatible = "st,24c64", "atmel,24c64";
     55		reg = <0x54>;
     56		pagesize = <32>;
     57	};
     58};
     59
     60&i2c1 {
     61	status = "okay";
     62};
     63
     64&i2c2 {
     65	status = "okay";
     66};
     67
     68&i2c3 {
     69	status = "okay";
     70};
     71
     72&sd {
     73	status = "okay";
     74};
     75
     76&usb2 {
     77	status = "okay";
     78};
     79
     80&usb3 {
     81	status = "okay";
     82};
     83
     84&eth {
     85	status = "okay";
     86	phy-handle = <&ethphy>;
     87};
     88
     89&mdio {
     90	ethphy: ethernet-phy@1 {
     91		reg = <1>;
     92	};
     93};
     94
     95&usb0 {
     96	status = "okay";
     97};
     98
     99&usb1 {
    100	status = "okay";
    101};