cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

uniphier-pro4-ref.dts (1400B)

      1// SPDX-License-Identifier: GPL-2.0+ OR MIT
      2//
      3// Device Tree Source for UniPhier Pro4 Reference Board
      4//
      5// Copyright (C) 2015-2016 Socionext Inc.
      6//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
      7
      8/dts-v1/;
      9#include "uniphier-pro4.dtsi"
     10#include "uniphier-ref-daughter.dtsi"
     11#include "uniphier-support-card.dtsi"
     12
     13/ {
     14	model = "UniPhier Pro4 Reference Board";
     15	compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4";
     16
     17	chosen {
     18		stdout-path = "serial0:115200n8";
     19	};
     20
     21	aliases {
     22		serial0 = &serial0;
     23		serial1 = &serial1;
     24		serial2 = &serial2;
     25		serial3 = &serialsc;
     26		i2c0 = &i2c0;
     27		i2c1 = &i2c1;
     28		i2c2 = &i2c2;
     29		i2c3 = &i2c3;
     30		i2c5 = &i2c5;
     31		i2c6 = &i2c6;
     32		ethernet0 = &eth;
     33	};
     34
     35	memory@80000000 {
     36		device_type = "memory";
     37		reg = <0x80000000 0x40000000>;
     38	};
     39};
     40
     41&ethsc {
     42	interrupts = <2 8>;
     43};
     44
     45&serialsc {
     46	interrupts = <2 8>;
     47};
     48
     49&serial0 {
     50	status = "okay";
     51};
     52
     53&serial1 {
     54	status = "okay";
     55};
     56
     57&serial2 {
     58	status = "okay";
     59};
     60
     61&gpio {
     62	xirq2 {
     63		gpio-hog;
     64		gpios = <UNIPHIER_GPIO_IRQ(2) 0>;
     65		input;
     66	};
     67};
     68
     69&i2c0 {
     70	status = "okay";
     71};
     72
     73&sd {
     74	status = "okay";
     75};
     76
     77&usb2 {
     78	status = "okay";
     79};
     80
     81&usb3 {
     82	status = "okay";
     83};
     84
     85&eth {
     86	status = "okay";
     87	phy-handle = <&ethphy>;
     88};
     89
     90&mdio {
     91	ethphy: ethernet-phy@0 {
     92		reg = <0>;
     93	};
     94};
     95
     96&usb0 {
     97	status = "okay";
     98};
     99
    100&usb1 {
    101	status = "okay";
    102};
    103
    104&nand {
    105	status = "okay";
    106
    107	nand@0 {
    108		reg = <0>;
    109	};
    110};