cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

uniphier-pxs2-gentil.dts (1444B)

      1// SPDX-License-Identifier: GPL-2.0+ OR MIT
      2//
      3// Device Tree Source for UniPhier PXs2 Gentil Board
      4//
      5// Copyright (C) 2015-2016 Socionext Inc.
      6//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
      7
      8/dts-v1/;
      9#include "uniphier-pxs2.dtsi"
     10
     11/ {
     12	model = "UniPhier PXs2 Gentil Board";
     13	compatible = "socionext,uniphier-pxs2-gentil",
     14		     "socionext,uniphier-pxs2";
     15
     16	chosen {
     17		stdout-path = "serial0:115200n8";
     18	};
     19
     20	aliases {
     21		serial0 = &serial2;
     22		serial1 = &serial0;
     23		serial2 = &serial1;
     24		i2c0 = &i2c0;
     25		i2c2 = &i2c2;
     26		i2c4 = &i2c4;
     27		i2c5 = &i2c5;
     28		i2c6 = &i2c6;
     29		ethernet0 = &eth;
     30	};
     31
     32	memory@80000000 {
     33		device_type = "memory";
     34		reg = <0x80000000 0x80000000>;
     35	};
     36
     37	sound {
     38		compatible = "audio-graph-card";
     39		label = "UniPhier PXs2";
     40		dais = <&i2s_port2>;
     41	};
     42};
     43
     44&serial2 {
     45	status = "okay";
     46};
     47
     48&i2c0 {
     49	status = "okay";
     50
     51	eeprom@54 {
     52		compatible = "st,24c64", "atmel,24c64";
     53		reg = <0x54>;
     54		pagesize = <32>;
     55	};
     56};
     57
     58&i2s_aux {
     59	dai-format = "i2s";
     60	remote-endpoint = <&wm_speaker>;
     61};
     62
     63&i2c2 {
     64	status = "okay";
     65
     66	wm8960@1a {
     67		compatible = "wlf,wm8960";
     68		reg = <0x1a>;
     69		#sound-dai-cells = <0>;
     70
     71		port@0 {
     72			wm_speaker: endpoint {
     73				dai-format = "i2s";
     74				remote-endpoint = <&i2s_aux>;
     75			};
     76		};
     77	};
     78};
     79
     80&emmc {
     81	status = "okay";
     82};
     83
     84&eth {
     85	status = "okay";
     86	phy-handle = <&ethphy>;
     87};
     88
     89&mdio {
     90	ethphy: ethernet-phy@1 {
     91		reg = <1>;
     92	};
     93};
     94
     95&usb0 {
     96	status = "okay";
     97};
     98
     99&usb1 {
    100	status = "okay";
    101};