cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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versatile-pb.dts (2802B)

      1// SPDX-License-Identifier: GPL-2.0
      2#include "versatile-ab.dts"
      3
      4/ {
      5	model = "ARM Versatile PB";
      6	compatible = "arm,versatile-pb";
      7
      8	amba {
      9		/* The Versatile PB is using more SIC IRQ lines than the AB */
     10		sic: interrupt-controller@10003000 {
     11			clear-mask = <0xffffffff>;
     12			/*
     13			 * Valid interrupt lines mask according to
     14			 * figure 3-30 page 3-74 of ARM DUI 0224B
     15			 */
     16			valid-mask = <0x7fe003ff>;
     17		};
     18
     19		gpio2: gpio@101e6000 {
     20			compatible = "arm,pl061", "arm,primecell";
     21			reg = <0x101e6000 0x1000>;
     22			interrupts = <8>;
     23			gpio-controller;
     24			#gpio-cells = <2>;
     25			interrupt-controller;
     26			#interrupt-cells = <2>;
     27			clocks = <&pclk>;
     28			clock-names = "apb_pclk";
     29		};
     30
     31		gpio3: gpio@101e7000 {
     32			compatible = "arm,pl061", "arm,primecell";
     33			reg = <0x101e7000 0x1000>;
     34			interrupts = <9>;
     35			gpio-controller;
     36			#gpio-cells = <2>;
     37			interrupt-controller;
     38			#interrupt-cells = <2>;
     39			clocks = <&pclk>;
     40			clock-names = "apb_pclk";
     41		};
     42
     43		pci@10001000 {
     44			compatible = "arm,versatile-pci";
     45			device_type = "pci";
     46			reg = <0x10001000 0x1000
     47			       0x41000000 0x10000
     48			       0x42000000 0x100000>;
     49			bus-range = <0 0xff>;
     50			#address-cells = <3>;
     51			#size-cells = <2>;
     52			#interrupt-cells = <1>;
     53
     54			ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000   /* downstream I/O */
     55				  0x02000000 0 0x50000000 0x50000000 0 0x10000000   /* non-prefetchable memory */
     56				  0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
     57
     58			interrupt-map-mask = <0x1800 0 0 7>;
     59			interrupt-map = <0x1800 0 0 1 &sic 28
     60					 0x1800 0 0 2 &sic 29
     61					 0x1800 0 0 3 &sic 30
     62					 0x1800 0 0 4 &sic 27
     63
     64					 0x1000 0 0 1 &sic 27
     65					 0x1000 0 0 2 &sic 28
     66					 0x1000 0 0 3 &sic 29
     67					 0x1000 0 0 4 &sic 30
     68
     69					 0x0800 0 0 1 &sic 30
     70					 0x0800 0 0 2 &sic 27
     71					 0x0800 0 0 3 &sic 28
     72					 0x0800 0 0 4 &sic 29
     73
     74					 0x0000 0 0 1 &sic 29
     75					 0x0000 0 0 2 &sic 30
     76					 0x0000 0 0 3 &sic 27
     77					 0x0000 0 0 4 &sic 28>;
     78		};
     79
     80		fpga {
     81			mmc@5000 {
     82				/*
     83				 * Overrides the interrupt assignment from
     84				 * the Versatile AB board file.
     85				 */
     86				interrupts-extended = <&sic 22 &sic 23>;
     87			};
     88			uart@9000 {
     89				compatible = "arm,pl011", "arm,primecell";
     90				reg = <0x9000 0x1000>;
     91				interrupt-parent = <&sic>;
     92				interrupts = <6>;
     93				clocks = <&xtal24mhz>, <&pclk>;
     94				clock-names = "uartclk", "apb_pclk";
     95			};
     96			sci@a000 {
     97				compatible = "arm,primecell";
     98				reg = <0xa000 0x1000>;
     99				interrupt-parent = <&sic>;
    100				interrupts = <5>;
    101				clocks = <&xtal24mhz>;
    102				clock-names = "apb_pclk";
    103			};
    104			mmc@b000 {
    105				compatible = "arm,pl180", "arm,primecell";
    106				reg = <0xb000 0x1000>;
    107				interrupt-parent = <&sic>;
    108				interrupts = <1>, <2>;
    109				clocks = <&xtal24mhz>, <&pclk>;
    110				clock-names = "mclk", "apb_pclk";
    111			};
    112		};
    113	};
    114};