vexpress-v2p-ca9.dts (6939B)
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * ARM Ltd. Versatile Express 4 * 5 * CoreTile Express A9x4 6 * Cortex-A9 MPCore (V2P-CA9) 7 * 8 * HBI-0191B 9 */ 10 11/dts-v1/; 12#include "vexpress-v2m.dtsi" 13 14/ { 15 model = "V2P-CA9"; 16 arm,hbi = <0x191>; 17 arm,vexpress,site = <0xf>; 18 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; 19 interrupt-parent = <&gic>; 20 #address-cells = <1>; 21 #size-cells = <1>; 22 23 chosen { }; 24 25 aliases { 26 serial0 = &v2m_serial0; 27 serial1 = &v2m_serial1; 28 serial2 = &v2m_serial2; 29 serial3 = &v2m_serial3; 30 i2c0 = &v2m_i2c_dvi; 31 i2c1 = &v2m_i2c_pcie; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 A9_0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a9"; 41 reg = <0>; 42 next-level-cache = <&L2>; 43 }; 44 45 A9_1: cpu@1 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a9"; 48 reg = <1>; 49 next-level-cache = <&L2>; 50 }; 51 52 A9_2: cpu@2 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a9"; 55 reg = <2>; 56 next-level-cache = <&L2>; 57 }; 58 59 A9_3: cpu@3 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a9"; 62 reg = <3>; 63 next-level-cache = <&L2>; 64 }; 65 }; 66 67 memory@60000000 { 68 device_type = "memory"; 69 reg = <0x60000000 0x40000000>; 70 }; 71 72 reserved-memory { 73 #address-cells = <1>; 74 #size-cells = <1>; 75 ranges; 76 77 /* Chipselect 3 is physically at 0x4c000000 */ 78 vram: vram@4c000000 { 79 /* 8 MB of designated video RAM */ 80 compatible = "shared-dma-pool"; 81 reg = <0x4c000000 0x00800000>; 82 no-map; 83 }; 84 }; 85 86 clcd@10020000 { 87 compatible = "arm,pl111", "arm,primecell"; 88 reg = <0x10020000 0x1000>; 89 interrupt-names = "combined"; 90 interrupts = <0 44 4>; 91 clocks = <&oscclk1>, <&oscclk2>; 92 clock-names = "clcdclk", "apb_pclk"; 93 /* 1024x768 16bpp @65MHz */ 94 max-memory-bandwidth = <95000000>; 95 96 port { 97 clcd_pads_ct: endpoint { 98 remote-endpoint = <&dvi_bridge_in_ct>; 99 arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 100 }; 101 }; 102 }; 103 104 memory-controller@100e0000 { 105 compatible = "arm,pl341", "arm,primecell"; 106 reg = <0x100e0000 0x1000>; 107 clocks = <&oscclk2>; 108 clock-names = "apb_pclk"; 109 }; 110 111 memory-controller@100e1000 { 112 compatible = "arm,pl354", "arm,primecell"; 113 reg = <0x100e1000 0x1000>; 114 interrupts = <0 45 4>, 115 <0 46 4>; 116 clocks = <&oscclk2>; 117 clock-names = "apb_pclk"; 118 }; 119 120 timer@100e4000 { 121 compatible = "arm,sp804", "arm,primecell"; 122 reg = <0x100e4000 0x1000>; 123 interrupts = <0 48 4>, 124 <0 49 4>; 125 clocks = <&oscclk2>, <&oscclk2>, <&oscclk2>; 126 clock-names = "timer0clk", "timer1clk", "apb_pclk"; 127 status = "disabled"; 128 }; 129 130 watchdog@100e5000 { 131 compatible = "arm,sp805", "arm,primecell"; 132 reg = <0x100e5000 0x1000>; 133 interrupts = <0 51 4>; 134 clocks = <&oscclk2>, <&oscclk2>; 135 clock-names = "wdog_clk", "apb_pclk"; 136 }; 137 138 scu@1e000000 { 139 compatible = "arm,cortex-a9-scu"; 140 reg = <0x1e000000 0x58>; 141 }; 142 143 timer@1e000600 { 144 compatible = "arm,cortex-a9-twd-timer"; 145 reg = <0x1e000600 0x20>; 146 interrupts = <1 13 0xf04>; 147 }; 148 149 watchdog@1e000620 { 150 compatible = "arm,cortex-a9-twd-wdt"; 151 reg = <0x1e000620 0x20>; 152 interrupts = <1 14 0xf04>; 153 }; 154 155 gic: interrupt-controller@1e001000 { 156 compatible = "arm,cortex-a9-gic"; 157 #interrupt-cells = <3>; 158 #address-cells = <0>; 159 interrupt-controller; 160 reg = <0x1e001000 0x1000>, 161 <0x1e000100 0x100>; 162 }; 163 164 L2: cache-controller@1e00a000 { 165 compatible = "arm,pl310-cache"; 166 reg = <0x1e00a000 0x1000>; 167 interrupts = <0 43 4>; 168 cache-unified; 169 cache-level = <2>; 170 arm,data-latency = <1 1 1>; 171 arm,tag-latency = <1 1 1>; 172 }; 173 174 pmu { 175 compatible = "arm,cortex-a9-pmu"; 176 interrupts = <0 60 4>, 177 <0 61 4>, 178 <0 62 4>, 179 <0 63 4>; 180 interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; 181 182 }; 183 184 dcc { 185 compatible = "arm,vexpress,config-bus"; 186 arm,vexpress,config-bridge = <&v2m_sysreg>; 187 188 oscclk0: extsaxiclk { 189 /* ACLK clock to the AXI master port on the test chip */ 190 compatible = "arm,vexpress-osc"; 191 arm,vexpress-sysreg,func = <1 0>; 192 freq-range = <30000000 50000000>; 193 #clock-cells = <0>; 194 clock-output-names = "extsaxiclk"; 195 }; 196 197 oscclk1: clcdclk { 198 /* Reference clock for the CLCD */ 199 compatible = "arm,vexpress-osc"; 200 arm,vexpress-sysreg,func = <1 1>; 201 freq-range = <10000000 80000000>; 202 #clock-cells = <0>; 203 clock-output-names = "clcdclk"; 204 }; 205 206 smbclk: oscclk2: tcrefclk { 207 /* Reference clock for the test chip internal PLLs */ 208 compatible = "arm,vexpress-osc"; 209 arm,vexpress-sysreg,func = <1 2>; 210 freq-range = <33000000 100000000>; 211 #clock-cells = <0>; 212 clock-output-names = "tcrefclk"; 213 }; 214 215 volt-vd10 { 216 /* Test Chip internal logic voltage */ 217 compatible = "arm,vexpress-volt"; 218 arm,vexpress-sysreg,func = <2 0>; 219 regulator-name = "VD10"; 220 regulator-always-on; 221 label = "VD10"; 222 }; 223 224 volt-vd10-s2 { 225 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ 226 compatible = "arm,vexpress-volt"; 227 arm,vexpress-sysreg,func = <2 1>; 228 regulator-name = "VD10_S2"; 229 regulator-always-on; 230 label = "VD10_S2"; 231 }; 232 233 volt-vd10-s3 { 234 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ 235 compatible = "arm,vexpress-volt"; 236 arm,vexpress-sysreg,func = <2 2>; 237 regulator-name = "VD10_S3"; 238 regulator-always-on; 239 label = "VD10_S3"; 240 }; 241 242 volt-vcc1v8 { 243 /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ 244 compatible = "arm,vexpress-volt"; 245 arm,vexpress-sysreg,func = <2 3>; 246 regulator-name = "VCC1V8"; 247 regulator-always-on; 248 label = "VCC1V8"; 249 }; 250 251 volt-ddr2vtt { 252 /* DDR2 SDRAM VTT termination voltage */ 253 compatible = "arm,vexpress-volt"; 254 arm,vexpress-sysreg,func = <2 4>; 255 regulator-name = "DDR2VTT"; 256 regulator-always-on; 257 label = "DDR2VTT"; 258 }; 259 260 volt-vcc3v3 { 261 /* Local board supply for miscellaneous logic external to the Test Chip */ 262 arm,vexpress-sysreg,func = <2 5>; 263 compatible = "arm,vexpress-volt"; 264 regulator-name = "VCC3V3"; 265 regulator-always-on; 266 label = "VCC3V3"; 267 }; 268 269 amp-vd10-s2 { 270 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ 271 compatible = "arm,vexpress-amp"; 272 arm,vexpress-sysreg,func = <3 0>; 273 label = "VD10_S2"; 274 }; 275 276 amp-vd10-s3 { 277 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ 278 compatible = "arm,vexpress-amp"; 279 arm,vexpress-sysreg,func = <3 1>; 280 label = "VD10_S3"; 281 }; 282 283 power-vd10-s2 { 284 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ 285 compatible = "arm,vexpress-power"; 286 arm,vexpress-sysreg,func = <12 0>; 287 label = "PVD10_S2"; 288 }; 289 290 power-vd10-s3 { 291 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ 292 compatible = "arm,vexpress-power"; 293 arm,vexpress-sysreg,func = <12 1>; 294 label = "PVD10_S3"; 295 }; 296 }; 297 298 site2: hsb@e0000000 { 299 compatible = "simple-bus"; 300 #address-cells = <1>; 301 #size-cells = <1>; 302 ranges = <0 0xe0000000 0x20000000>; 303 #interrupt-cells = <1>; 304 interrupt-map-mask = <0 3>; 305 interrupt-map = <0 0 &gic 0 36 4>, 306 <0 1 &gic 0 37 4>, 307 <0 2 &gic 0 38 4>, 308 <0 3 &gic 0 39 4>; 309 }; 310};