zynq-zc706.dts (5279B)
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2011 - 2014 Xilinx 4 * Copyright (C) 2012 National Instruments Corp. 5 */ 6/dts-v1/; 7#include "zynq-7000.dtsi" 8 9/ { 10 model = "Xilinx ZC706 board"; 11 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; 12 13 aliases { 14 ethernet0 = &gem0; 15 i2c0 = &i2c0; 16 serial0 = &uart1; 17 mmc0 = &sdhci0; 18 }; 19 20 memory@0 { 21 device_type = "memory"; 22 reg = <0x0 0x40000000>; 23 }; 24 25 chosen { 26 bootargs = ""; 27 stdout-path = "serial0:115200n8"; 28 }; 29 30 usb_phy0: phy0 { 31 compatible = "usb-nop-xceiv"; 32 #phy-cells = <0>; 33 }; 34}; 35 36&clkc { 37 ps-clk-frequency = <33333333>; 38}; 39 40&gem0 { 41 status = "okay"; 42 phy-mode = "rgmii-id"; 43 phy-handle = <ðernet_phy>; 44 pinctrl-names = "default"; 45 pinctrl-0 = <&pinctrl_gem0_default>; 46 47 ethernet_phy: ethernet-phy@7 { 48 reg = <7>; 49 device_type = "ethernet-phy"; 50 }; 51}; 52 53&gpio0 { 54 pinctrl-names = "default"; 55 pinctrl-0 = <&pinctrl_gpio0_default>; 56}; 57 58&i2c0 { 59 status = "okay"; 60 clock-frequency = <400000>; 61 pinctrl-names = "default"; 62 pinctrl-0 = <&pinctrl_i2c0_default>; 63 64 i2c-mux@74 { 65 compatible = "nxp,pca9548"; 66 #address-cells = <1>; 67 #size-cells = <0>; 68 reg = <0x74>; 69 70 i2c@0 { 71 #address-cells = <1>; 72 #size-cells = <0>; 73 reg = <0>; 74 si570: clock-generator@5d { 75 #clock-cells = <0>; 76 compatible = "silabs,si570"; 77 temperature-stability = <50>; 78 reg = <0x5d>; 79 factory-fout = <156250000>; 80 clock-frequency = <148500000>; 81 }; 82 }; 83 84 i2c@1 { 85 #address-cells = <1>; 86 #size-cells = <0>; 87 reg = <1>; 88 adv7511: hdmi-tx@39 { 89 compatible = "adi,adv7511"; 90 reg = <0x39>; 91 adi,input-depth = <8>; 92 adi,input-colorspace = "yuv422"; 93 adi,input-clock = "1x"; 94 adi,input-style = <3>; 95 adi,input-justification = "evenly"; 96 }; 97 }; 98 99 i2c@2 { 100 #address-cells = <1>; 101 #size-cells = <0>; 102 reg = <2>; 103 eeprom@54 { 104 compatible = "atmel,24c08"; 105 reg = <0x54>; 106 }; 107 }; 108 109 i2c@3 { 110 #address-cells = <1>; 111 #size-cells = <0>; 112 reg = <3>; 113 gpio@21 { 114 compatible = "ti,tca6416"; 115 reg = <0x21>; 116 gpio-controller; 117 #gpio-cells = <2>; 118 }; 119 }; 120 121 i2c@4 { 122 #address-cells = <1>; 123 #size-cells = <0>; 124 reg = <4>; 125 rtc@51 { 126 compatible = "nxp,pcf8563"; 127 reg = <0x51>; 128 }; 129 }; 130 131 i2c@7 { 132 #address-cells = <1>; 133 #size-cells = <0>; 134 reg = <7>; 135 ucd90120@65 { 136 compatible = "ti,ucd90120"; 137 reg = <0x65>; 138 }; 139 }; 140 }; 141}; 142 143&pinctrl0 { 144 pinctrl_gem0_default: gem0-default { 145 mux { 146 function = "ethernet0"; 147 groups = "ethernet0_0_grp"; 148 }; 149 150 conf { 151 groups = "ethernet0_0_grp"; 152 slew-rate = <0>; 153 io-standard = <4>; 154 }; 155 156 conf-rx { 157 pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; 158 bias-high-impedance; 159 low-power-disable; 160 }; 161 162 conf-tx { 163 pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; 164 low-power-enable; 165 bias-disable; 166 }; 167 168 mux-mdio { 169 function = "mdio0"; 170 groups = "mdio0_0_grp"; 171 }; 172 173 conf-mdio { 174 groups = "mdio0_0_grp"; 175 slew-rate = <0>; 176 io-standard = <1>; 177 bias-disable; 178 }; 179 }; 180 181 pinctrl_gpio0_default: gpio0-default { 182 mux { 183 function = "gpio0"; 184 groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; 185 }; 186 187 conf { 188 groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; 189 slew-rate = <0>; 190 io-standard = <1>; 191 }; 192 193 conf-pull-up { 194 pins = "MIO46", "MIO47"; 195 bias-pull-up; 196 }; 197 198 conf-pull-none { 199 pins = "MIO7"; 200 bias-disable; 201 }; 202 }; 203 204 pinctrl_i2c0_default: i2c0-default { 205 mux { 206 groups = "i2c0_10_grp"; 207 function = "i2c0"; 208 }; 209 210 conf { 211 groups = "i2c0_10_grp"; 212 bias-pull-up; 213 slew-rate = <0>; 214 io-standard = <1>; 215 }; 216 }; 217 218 pinctrl_sdhci0_default: sdhci0-default { 219 mux { 220 groups = "sdio0_2_grp"; 221 function = "sdio0"; 222 }; 223 224 conf { 225 groups = "sdio0_2_grp"; 226 slew-rate = <0>; 227 io-standard = <1>; 228 bias-disable; 229 }; 230 231 mux-cd { 232 groups = "gpio0_14_grp"; 233 function = "sdio0_cd"; 234 }; 235 236 conf-cd { 237 groups = "gpio0_14_grp"; 238 bias-high-impedance; 239 bias-pull-up; 240 slew-rate = <0>; 241 io-standard = <1>; 242 }; 243 244 mux-wp { 245 groups = "gpio0_15_grp"; 246 function = "sdio0_wp"; 247 }; 248 249 conf-wp { 250 groups = "gpio0_15_grp"; 251 bias-high-impedance; 252 bias-pull-up; 253 slew-rate = <0>; 254 io-standard = <1>; 255 }; 256 }; 257 258 pinctrl_uart1_default: uart1-default { 259 mux { 260 groups = "uart1_10_grp"; 261 function = "uart1"; 262 }; 263 264 conf { 265 groups = "uart1_10_grp"; 266 slew-rate = <0>; 267 io-standard = <1>; 268 }; 269 270 conf-rx { 271 pins = "MIO49"; 272 bias-high-impedance; 273 }; 274 275 conf-tx { 276 pins = "MIO48"; 277 bias-disable; 278 }; 279 }; 280 281 pinctrl_usb0_default: usb0-default { 282 mux { 283 groups = "usb0_0_grp"; 284 function = "usb0"; 285 }; 286 287 conf { 288 groups = "usb0_0_grp"; 289 slew-rate = <0>; 290 io-standard = <1>; 291 }; 292 293 conf-rx { 294 pins = "MIO29", "MIO31", "MIO36"; 295 bias-high-impedance; 296 }; 297 298 conf-tx { 299 pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", 300 "MIO35", "MIO37", "MIO38", "MIO39"; 301 bias-disable; 302 }; 303 }; 304}; 305 306&sdhci0 { 307 status = "okay"; 308 pinctrl-names = "default"; 309 pinctrl-0 = <&pinctrl_sdhci0_default>; 310}; 311 312&uart1 { 313 status = "okay"; 314 pinctrl-names = "default"; 315 pinctrl-0 = <&pinctrl_uart1_default>; 316}; 317 318&usb0 { 319 status = "okay"; 320 dr_mode = "host"; 321 usb-phy = <&usb_phy0>; 322 pinctrl-names = "default"; 323 pinctrl-0 = <&pinctrl_usb0_default>; 324};