cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

zynq-zc770-xm010.dts (1369B)

      1// SPDX-License-Identifier: GPL-2.0+
      2/*
      3 * Xilinx ZC770 XM010 board DTS
      4 *
      5 * Copyright (C) 2013-2018 Xilinx, Inc.
      6 */
      7/dts-v1/;
      8#include "zynq-7000.dtsi"
      9
     10/ {
     11	model = "Xilinx ZC770 XM010 board";
     12	compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
     13
     14	aliases {
     15		ethernet0 = &gem0;
     16		i2c0 = &i2c0;
     17		serial0 = &uart1;
     18		spi1 = &spi1;
     19	};
     20
     21	chosen {
     22		bootargs = "";
     23		stdout-path = "serial0:115200n8";
     24	};
     25
     26	memory@0 {
     27		device_type = "memory";
     28		reg = <0x0 0x40000000>;
     29	};
     30
     31	usb_phy0: phy0 {
     32		compatible = "usb-nop-xceiv";
     33		#phy-cells = <0>;
     34	};
     35};
     36
     37&can0 {
     38	status = "okay";
     39};
     40
     41&gem0 {
     42	status = "okay";
     43	phy-mode = "rgmii-id";
     44	phy-handle = <&ethernet_phy>;
     45
     46	ethernet_phy: ethernet-phy@7 {
     47		reg = <7>;
     48		device_type = "ethernet-phy";
     49	};
     50};
     51
     52&i2c0 {
     53	status = "okay";
     54	clock-frequency = <400000>;
     55
     56	eeprom: eeprom@52 {
     57		compatible = "atmel,24c02";
     58		reg = <0x52>;
     59	};
     60
     61};
     62
     63&sdhci0 {
     64	status = "okay";
     65};
     66
     67&spi1 {
     68	status = "okay";
     69	num-cs = <4>;
     70	is-decoded-cs = <0>;
     71	flash@1 {
     72		compatible = "sst25wf080", "jedec,spi-nor";
     73		reg = <1>;
     74		spi-max-frequency = <1000000>;
     75		partitions {
     76			compatible = "fixed-partitions";
     77			#address-cells = <1>;
     78			#size-cells = <1>;
     79			partition@0 {
     80				label = "data";
     81				reg = <0x0 0x100000>;
     82			};
     83		};
     84	};
     85};
     86
     87&uart1 {
     88	status = "okay";
     89};
     90
     91&usb0 {
     92	status = "okay";
     93	dr_mode = "host";
     94	usb-phy = <&usb_phy0>;
     95};