cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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zynq-zc770-xm013.dts (1189B)

      1// SPDX-License-Identifier: GPL-2.0+
      2/*
      3 * Xilinx ZC770 XM013 board DTS
      4 *
      5 * Copyright (C) 2013 Xilinx, Inc.
      6 */
      7/dts-v1/;
      8#include "zynq-7000.dtsi"
      9
     10/ {
     11	model = "Xilinx ZC770 XM013 board";
     12	compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
     13
     14	aliases {
     15		ethernet0 = &gem1;
     16		i2c0 = &i2c1;
     17		serial0 = &uart0;
     18		spi1 = &spi0;
     19	};
     20
     21	chosen {
     22		bootargs = "";
     23		stdout-path = "serial0:115200n8";
     24	};
     25
     26	memory@0 {
     27		device_type = "memory";
     28		reg = <0x0 0x40000000>;
     29	};
     30};
     31
     32&can1 {
     33	status = "okay";
     34};
     35
     36&gem1 {
     37	status = "okay";
     38	phy-mode = "rgmii-id";
     39	phy-handle = <&ethernet_phy>;
     40
     41	ethernet_phy: ethernet-phy@7 {
     42		reg = <7>;
     43		device_type = "ethernet-phy";
     44	};
     45};
     46
     47&i2c1 {
     48	status = "okay";
     49	clock-frequency = <400000>;
     50
     51	si570: clock-generator@55 {
     52		#clock-cells = <0>;
     53		compatible = "silabs,si570";
     54		temperature-stability = <50>;
     55		reg = <0x55>;
     56		factory-fout = <156250000>;
     57		clock-frequency = <148500000>;
     58	};
     59};
     60
     61&spi0 {
     62	status = "okay";
     63	num-cs = <4>;
     64	is-decoded-cs = <0>;
     65	eeprom: eeprom@2 {
     66		compatible = "atmel,at25";
     67		reg = <2>;
     68		spi-max-frequency = <1000000>;
     69		size = <8192>;
     70		address-width = <16>;
     71		pagesize = <32>;
     72	};
     73};
     74
     75&uart0 {
     76	status = "okay";
     77};