domain.h (3751B)
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * arch/arm/include/asm/domain.h 4 * 5 * Copyright (C) 1999 Russell King. 6 */ 7#ifndef __ASM_PROC_DOMAIN_H 8#define __ASM_PROC_DOMAIN_H 9 10#ifndef __ASSEMBLY__ 11#include <asm/barrier.h> 12#include <asm/thread_info.h> 13#endif 14 15/* 16 * Domain numbers 17 * 18 * DOMAIN_IO - domain 2 includes all IO only 19 * DOMAIN_USER - domain 1 includes all user memory only 20 * DOMAIN_KERNEL - domain 0 includes all kernel memory only 21 * 22 * The domain numbering depends on whether we support 36 physical 23 * address for I/O or not. Addresses above the 32 bit boundary can 24 * only be mapped using supersections and supersections can only 25 * be set for domain 0. We could just default to DOMAIN_IO as zero, 26 * but there may be systems with supersection support and no 36-bit 27 * addressing. In such cases, we want to map system memory with 28 * supersections to reduce TLB misses and footprint. 29 * 30 * 36-bit addressing and supersections are only available on 31 * CPUs based on ARMv6+ or the Intel XSC3 core. 32 */ 33#ifndef CONFIG_IO_36 34#define DOMAIN_KERNEL 0 35#define DOMAIN_USER 1 36#define DOMAIN_IO 2 37#else 38#define DOMAIN_KERNEL 2 39#define DOMAIN_USER 1 40#define DOMAIN_IO 0 41#endif 42#define DOMAIN_VECTORS 3 43 44/* 45 * Domain types 46 */ 47#define DOMAIN_NOACCESS 0 48#define DOMAIN_CLIENT 1 49#ifdef CONFIG_CPU_USE_DOMAINS 50#define DOMAIN_MANAGER 3 51#else 52#define DOMAIN_MANAGER 1 53#endif 54 55#define domain_mask(dom) ((3) << (2 * (dom))) 56#define domain_val(dom,type) ((type) << (2 * (dom))) 57 58#ifdef CONFIG_CPU_SW_DOMAIN_PAN 59#define DACR_INIT \ 60 (domain_val(DOMAIN_USER, DOMAIN_NOACCESS) | \ 61 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ 62 domain_val(DOMAIN_IO, DOMAIN_CLIENT) | \ 63 domain_val(DOMAIN_VECTORS, DOMAIN_CLIENT)) 64#else 65#define DACR_INIT \ 66 (domain_val(DOMAIN_USER, DOMAIN_CLIENT) | \ 67 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ 68 domain_val(DOMAIN_IO, DOMAIN_CLIENT) | \ 69 domain_val(DOMAIN_VECTORS, DOMAIN_CLIENT)) 70#endif 71 72#define __DACR_DEFAULT \ 73 domain_val(DOMAIN_KERNEL, DOMAIN_CLIENT) | \ 74 domain_val(DOMAIN_IO, DOMAIN_CLIENT) | \ 75 domain_val(DOMAIN_VECTORS, DOMAIN_CLIENT) 76 77#define DACR_UACCESS_DISABLE \ 78 (__DACR_DEFAULT | domain_val(DOMAIN_USER, DOMAIN_NOACCESS)) 79#define DACR_UACCESS_ENABLE \ 80 (__DACR_DEFAULT | domain_val(DOMAIN_USER, DOMAIN_CLIENT)) 81 82#ifndef __ASSEMBLY__ 83 84#ifdef CONFIG_CPU_CP15_MMU 85static __always_inline unsigned int get_domain(void) 86{ 87 unsigned int domain; 88 89 asm( 90 "mrc p15, 0, %0, c3, c0 @ get domain" 91 : "=r" (domain) 92 : "m" (current_thread_info()->cpu_domain)); 93 94 return domain; 95} 96 97static __always_inline void set_domain(unsigned int val) 98{ 99 asm volatile( 100 "mcr p15, 0, %0, c3, c0 @ set domain" 101 : : "r" (val) : "memory"); 102 isb(); 103} 104#else 105static __always_inline unsigned int get_domain(void) 106{ 107 return 0; 108} 109 110static __always_inline void set_domain(unsigned int val) 111{ 112} 113#endif 114 115#ifdef CONFIG_CPU_USE_DOMAINS 116#define modify_domain(dom,type) \ 117 do { \ 118 unsigned int domain = get_domain(); \ 119 domain &= ~domain_mask(dom); \ 120 domain = domain | domain_val(dom, type); \ 121 set_domain(domain); \ 122 } while (0) 123 124#else 125static inline void modify_domain(unsigned dom, unsigned type) { } 126#endif 127 128/* 129 * Generate the T (user) versions of the LDR/STR and related 130 * instructions (inline assembly) 131 */ 132#ifdef CONFIG_CPU_USE_DOMAINS 133#define TUSER(instr) TUSERCOND(instr, ) 134#define TUSERCOND(instr, cond) #instr "t" #cond 135#else 136#define TUSER(instr) TUSERCOND(instr, ) 137#define TUSERCOND(instr, cond) #instr #cond 138#endif 139 140#else /* __ASSEMBLY__ */ 141 142/* 143 * Generate the T (user) versions of the LDR/STR and related 144 * instructions 145 */ 146#ifdef CONFIG_CPU_USE_DOMAINS 147#define TUSER(instr) instr ## t 148#else 149#define TUSER(instr) instr 150#endif 151 152#endif /* __ASSEMBLY__ */ 153 154#endif /* !__ASM_PROC_DOMAIN_H */