cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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kgdb.h (2783B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * ARM KGDB support
      4 *
      5 * Author: Deepak Saxena <dsaxena@mvista.com>
      6 *
      7 * Copyright (C) 2002 MontaVista Software Inc.
      8 *
      9 */
     10
     11#ifndef __ARM_KGDB_H__
     12#define __ARM_KGDB_H__
     13
     14#include <linux/ptrace.h>
     15#include <asm/opcodes.h>
     16
     17/*
     18 * GDB assumes that we're a user process being debugged, so
     19 * it will send us an SWI command to write into memory as the
     20 * debug trap. When an SWI occurs, the next instruction addr is
     21 * placed into R14_svc before jumping to the vector trap.
     22 * This doesn't work for kernel debugging as we are already in SVC
     23 * we would loose the kernel's LR, which is a bad thing. This
     24 * is  bad thing.
     25 *
     26 * By doing this as an undefined instruction trap, we force a mode
     27 * switch from SVC to UND mode, allowing us to save full kernel state.
     28 *
     29 * We also define a KGDB_COMPILED_BREAK which can be used to compile
     30 * in breakpoints. This is important for things like sysrq-G and for
     31 * the initial breakpoint from trap_init().
     32 *
     33 * Note to ARM HW designers: Add real trap support like SH && PPC to
     34 * make our lives much much simpler. :)
     35 */
     36#define BREAK_INSTR_SIZE	4
     37#define GDB_BREAKINST		0xef9f0001
     38#define KGDB_BREAKINST		0xe7ffdefe
     39#define KGDB_COMPILED_BREAK	0xe7ffdeff
     40#define CACHE_FLUSH_IS_SAFE	1
     41
     42#ifndef	__ASSEMBLY__
     43
     44static inline void arch_kgdb_breakpoint(void)
     45{
     46	asm(__inst_arm(0xe7ffdeff));
     47}
     48
     49extern void kgdb_handle_bus_error(void);
     50extern int kgdb_fault_expected;
     51
     52#endif /* !__ASSEMBLY__ */
     53
     54/*
     55 * From Kevin Hilman:
     56 *
     57 * gdb is expecting the following registers layout.
     58 *
     59 * r0-r15: 1 long word each
     60 * f0-f7:  unused, 3 long words each !!
     61 * fps:    unused, 1 long word
     62 * cpsr:   1 long word
     63 *
     64 * Even though f0-f7 and fps are not used, they need to be
     65 * present in the registers sent for correct processing in
     66 * the host-side gdb.
     67 *
     68 * In particular, it is crucial that CPSR is in the right place,
     69 * otherwise gdb will not be able to correctly interpret stepping over
     70 * conditional branches.
     71 */
     72#define _GP_REGS		16
     73#define _FP_REGS		8
     74#define _EXTRA_REGS		2
     75#define GDB_MAX_REGS		(_GP_REGS + (_FP_REGS * 3) + _EXTRA_REGS)
     76#define DBG_MAX_REG_NUM		(_GP_REGS + _FP_REGS + _EXTRA_REGS)
     77
     78#define KGDB_MAX_NO_CPUS	1
     79#define BUFMAX			400
     80#define NUMREGBYTES		(GDB_MAX_REGS << 2)
     81#define NUMCRITREGBYTES		(32 << 2)
     82
     83#define _R0			0
     84#define _R1			1
     85#define _R2			2
     86#define _R3			3
     87#define _R4			4
     88#define _R5			5
     89#define _R6			6
     90#define _R7			7
     91#define _R8			8
     92#define _R9			9
     93#define _R10			10
     94#define _FP			11
     95#define _IP			12
     96#define _SPT			13
     97#define _LR			14
     98#define _PC			15
     99#define _CPSR			(GDB_MAX_REGS - 1)
    100
    101/*
    102 * So that we can denote the end of a frame for tracing,
    103 * in the simple case:
    104 */
    105#define CFI_END_FRAME(func)	__CFI_END_FRAME(_PC, _SPT, func)
    106
    107#endif /* __ASM_KGDB_H__ */