cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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opcodes.h (8255B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 *  arch/arm/include/asm/opcodes.h
      4 */
      5
      6#ifndef __ASM_ARM_OPCODES_H
      7#define __ASM_ARM_OPCODES_H
      8
      9#ifndef __ASSEMBLY__
     10#include <linux/linkage.h>
     11extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
     12#endif
     13
     14#define ARM_OPCODE_CONDTEST_FAIL   0
     15#define ARM_OPCODE_CONDTEST_PASS   1
     16#define ARM_OPCODE_CONDTEST_UNCOND 2
     17
     18
     19/*
     20 * Assembler opcode byteswap helpers.
     21 * These are only intended for use by this header: don't use them directly,
     22 * because they will be suboptimal in most cases.
     23 */
     24#define ___asm_opcode_swab32(x) (	\
     25	  (((x) << 24) & 0xFF000000)	\
     26	| (((x) <<  8) & 0x00FF0000)	\
     27	| (((x) >>  8) & 0x0000FF00)	\
     28	| (((x) >> 24) & 0x000000FF)	\
     29)
     30#define ___asm_opcode_swab16(x) (	\
     31	  (((x) << 8) & 0xFF00)		\
     32	| (((x) >> 8) & 0x00FF)		\
     33)
     34#define ___asm_opcode_swahb32(x) (	\
     35	  (((x) << 8) & 0xFF00FF00)	\
     36	| (((x) >> 8) & 0x00FF00FF)	\
     37)
     38#define ___asm_opcode_swahw32(x) (	\
     39	  (((x) << 16) & 0xFFFF0000)	\
     40	| (((x) >> 16) & 0x0000FFFF)	\
     41)
     42#define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF)
     43#define ___asm_opcode_identity16(x) ((x) & 0xFFFF)
     44
     45
     46/*
     47 * Opcode byteswap helpers
     48 *
     49 * These macros help with converting instructions between a canonical integer
     50 * format and in-memory representation, in an endianness-agnostic manner.
     51 *
     52 * __mem_to_opcode_*() convert from in-memory representation to canonical form.
     53 * __opcode_to_mem_*() convert from canonical form to in-memory representation.
     54 *
     55 *
     56 * Canonical instruction representation:
     57 *
     58 *	ARM:		0xKKLLMMNN
     59 *	Thumb 16-bit:	0x0000KKLL, where KK < 0xE8
     60 *	Thumb 32-bit:	0xKKLLMMNN, where KK >= 0xE8
     61 *
     62 * There is no way to distinguish an ARM instruction in canonical representation
     63 * from a Thumb instruction (just as these cannot be distinguished in memory).
     64 * Where this distinction is important, it needs to be tracked separately.
     65 *
     66 * Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not
     67 * represent any valid Thumb-2 instruction.  For this range,
     68 * __opcode_is_thumb32() and __opcode_is_thumb16() will both be false.
     69 *
     70 * The ___asm variants are intended only for use by this header, in situations
     71 * involving inline assembler.  For .S files, the normal __opcode_*() macros
     72 * should do the right thing.
     73 */
     74#ifdef __ASSEMBLY__
     75
     76#define ___opcode_swab32(x) ___asm_opcode_swab32(x)
     77#define ___opcode_swab16(x) ___asm_opcode_swab16(x)
     78#define ___opcode_swahb32(x) ___asm_opcode_swahb32(x)
     79#define ___opcode_swahw32(x) ___asm_opcode_swahw32(x)
     80#define ___opcode_identity32(x) ___asm_opcode_identity32(x)
     81#define ___opcode_identity16(x) ___asm_opcode_identity16(x)
     82
     83#else /* ! __ASSEMBLY__ */
     84
     85#include <linux/types.h>
     86#include <linux/swab.h>
     87
     88#define ___opcode_swab32(x) swab32(x)
     89#define ___opcode_swab16(x) swab16(x)
     90#define ___opcode_swahb32(x) swahb32(x)
     91#define ___opcode_swahw32(x) swahw32(x)
     92#define ___opcode_identity32(x) ((u32)(x))
     93#define ___opcode_identity16(x) ((u16)(x))
     94
     95#endif /* ! __ASSEMBLY__ */
     96
     97
     98#ifdef CONFIG_CPU_ENDIAN_BE8
     99
    100#define __opcode_to_mem_arm(x) ___opcode_swab32(x)
    101#define __opcode_to_mem_thumb16(x) ___opcode_swab16(x)
    102#define __opcode_to_mem_thumb32(x) ___opcode_swahb32(x)
    103#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_swab32(x)
    104#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_swab16(x)
    105#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahb32(x)
    106
    107#else /* ! CONFIG_CPU_ENDIAN_BE8 */
    108
    109#define __opcode_to_mem_arm(x) ___opcode_identity32(x)
    110#define __opcode_to_mem_thumb16(x) ___opcode_identity16(x)
    111#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_identity32(x)
    112#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_identity16(x)
    113#ifdef CONFIG_CPU_ENDIAN_BE32
    114#ifndef __ASSEMBLY__
    115/*
    116 * On BE32 systems, using 32-bit accesses to store Thumb instructions will not
    117 * work in all cases, due to alignment constraints.  For now, a correct
    118 * version is not provided for BE32, but the prototype needs to be there
    119 * to compile patch.c.
    120 */
    121extern __u32 __opcode_to_mem_thumb32(__u32);
    122#endif
    123#else
    124#define __opcode_to_mem_thumb32(x) ___opcode_swahw32(x)
    125#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahw32(x)
    126#endif
    127
    128#endif /* ! CONFIG_CPU_ENDIAN_BE8 */
    129
    130#define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x)
    131#define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x)
    132#ifndef CONFIG_CPU_ENDIAN_BE32
    133#define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x)
    134#endif
    135
    136/* Operations specific to Thumb opcodes */
    137
    138/* Instruction size checks: */
    139#define __opcode_is_thumb32(x) (		\
    140	   ((x) & 0xF8000000) == 0xE8000000	\
    141	|| ((x) & 0xF0000000) == 0xF0000000	\
    142)
    143#define __opcode_is_thumb16(x) (					\
    144	   ((x) & 0xFFFF0000) == 0					\
    145	&& !(((x) & 0xF800) == 0xE800 || ((x) & 0xF000) == 0xF000)	\
    146)
    147
    148/* Operations to construct or split 32-bit Thumb instructions: */
    149#define __opcode_thumb32_first(x) (___opcode_identity16((x) >> 16))
    150#define __opcode_thumb32_second(x) (___opcode_identity16(x))
    151#define __opcode_thumb32_compose(first, second) (			\
    152	  (___opcode_identity32(___opcode_identity16(first)) << 16)	\
    153	| ___opcode_identity32(___opcode_identity16(second))		\
    154)
    155#define ___asm_opcode_thumb32_first(x) (___asm_opcode_identity16((x) >> 16))
    156#define ___asm_opcode_thumb32_second(x) (___asm_opcode_identity16(x))
    157#define ___asm_opcode_thumb32_compose(first, second) (			    \
    158	  (___asm_opcode_identity32(___asm_opcode_identity16(first)) << 16) \
    159	| ___asm_opcode_identity32(___asm_opcode_identity16(second))	    \
    160)
    161
    162/*
    163 * Opcode injection helpers
    164 *
    165 * In rare cases it is necessary to assemble an opcode which the
    166 * assembler does not support directly, or which would normally be
    167 * rejected because of the CFLAGS or AFLAGS used to build the affected
    168 * file.
    169 *
    170 * Before using these macros, consider carefully whether it is feasible
    171 * instead to change the build flags for your file, or whether it really
    172 * makes sense to support old assembler versions when building that
    173 * particular kernel feature.
    174 *
    175 * The macros defined here should only be used where there is no viable
    176 * alternative.
    177 *
    178 *
    179 * __inst_arm(x): emit the specified ARM opcode
    180 * __inst_thumb16(x): emit the specified 16-bit Thumb opcode
    181 * __inst_thumb32(x): emit the specified 32-bit Thumb opcode
    182 *
    183 * __inst_arm_thumb16(arm, thumb): emit either the specified arm or
    184 *	16-bit Thumb opcode, depending on whether an ARM or Thumb-2
    185 *	kernel is being built
    186 *
    187 * __inst_arm_thumb32(arm, thumb): emit either the specified arm or
    188 *	32-bit Thumb opcode, depending on whether an ARM or Thumb-2
    189 *	kernel is being built
    190 *
    191 *
    192 * Note that using these macros directly is poor practice.  Instead, you
    193 * should use them to define human-readable wrapper macros to encode the
    194 * instructions that you care about.  In code which might run on ARMv7 or
    195 * above, you can usually use the __inst_arm_thumb{16,32} macros to
    196 * specify the ARM and Thumb alternatives at the same time.  This ensures
    197 * that the correct opcode gets emitted depending on the instruction set
    198 * used for the kernel build.
    199 *
    200 * Look at opcodes-virt.h for an example of how to use these macros.
    201 */
    202#include <linux/stringify.h>
    203
    204#define __inst_arm(x) ___inst_arm(___asm_opcode_to_mem_arm(x))
    205#define __inst_thumb32(x) ___inst_thumb32(				\
    206	___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_first(x)),	\
    207	___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_second(x))	\
    208)
    209#define __inst_thumb16(x) ___inst_thumb16(___asm_opcode_to_mem_thumb16(x))
    210
    211#ifdef CONFIG_THUMB2_KERNEL
    212#define __inst_arm_thumb16(arm_opcode, thumb_opcode) \
    213	__inst_thumb16(thumb_opcode)
    214#define __inst_arm_thumb32(arm_opcode, thumb_opcode) \
    215	__inst_thumb32(thumb_opcode)
    216#else
    217#define __inst_arm_thumb16(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
    218#define __inst_arm_thumb32(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
    219#endif
    220
    221/* Helpers for the helpers.  Don't use these directly. */
    222#ifdef __ASSEMBLY__
    223#define ___inst_arm(x) .long x
    224#define ___inst_thumb16(x) .short x
    225#define ___inst_thumb32(first, second) .short first, second
    226#else
    227#define ___inst_arm(x) ".long " __stringify(x) "\n\t"
    228#define ___inst_thumb16(x) ".short " __stringify(x) "\n\t"
    229#define ___inst_thumb32(first, second) \
    230	".short " __stringify(first) ", " __stringify(second) "\n\t"
    231#endif
    232
    233#endif /* __ASM_ARM_OPCODES_H */