cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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swab.h (1005B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 *  arch/arm/include/asm/byteorder.h
      4 *
      5 * ARM Endian-ness.  In little endian mode, the data bus is connected such
      6 * that byte accesses appear as:
      7 *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
      8 * and word accesses (data or instruction) appear as:
      9 *  d0...d31
     10 *
     11 * When in big endian mode, byte accesses appear as:
     12 *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
     13 * and word accesses (data or instruction) appear as:
     14 *  d0...d31
     15 */
     16#ifndef __ASM_ARM_SWAB_H
     17#define __ASM_ARM_SWAB_H
     18
     19#include <uapi/asm/swab.h>
     20
     21#if __LINUX_ARM_ARCH__ >= 6
     22
     23static inline __attribute_const__ __u32 __arch_swahb32(__u32 x)
     24{
     25	__asm__ ("rev16 %0, %1" : "=r" (x) : "r" (x));
     26	return x;
     27}
     28#define __arch_swahb32 __arch_swahb32
     29#define __arch_swab16(x) ((__u16)__arch_swahb32(x))
     30
     31static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
     32{
     33	__asm__ ("rev %0, %1" : "=r" (x) : "r" (x));
     34	return x;
     35}
     36#define __arch_swab32 __arch_swab32
     37
     38#endif
     39#endif